• Journal of the Korean Society for Precision Engineering
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• v.28 no.8
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• pp.966-974
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• 2011

The use of ion beams in the micro/nano scale is greatly increased by technology development. Especially, focused ion beams (FIBs) have a great potential to fabricate the device in sub micro scale. Nevertheless, FIB has several limitations, surface swelling in low ion dose regime, precipitation of incident ions, and the redeposition effect due to the sputtered atoms. In this research, we demonstrate a way which can be used to fabricate mold structures on a silicon substrate using FIBs. For the purpose of the demonstration, two essential subjects are necessary. One is that focused ion beam diameter as well as shape has to be measured and verified. The other one is that the accurate rotational symmetric model of ion-solid interaction has to be mathematically developed. We apply those two, measured beam diameter and mathematical model, to fabricate optical lenses mold on silicon. The characteristics of silicon mold fabrication will be discussed as well as simulation results.

• Proceedings of the KSME Conference
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• 2000.04b
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• pp.428-433
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• 2000

The consolidation behavior of multicomponent particles prepared by the flame hydrolysis deposition process is examined to identify the effects of Si substrate temperature. To fabricate multi-component particles, a vapor-phase ternary mixture of $SiCl_4(100 cc/min),\;BCl_3(30cc/min)\;and\;POCl_3,(5cc/min)$ was fed into a coflow diffusion oxy-hydrogen flame burner. The doped silica soot bodies were deposited on silicon substrates under various deposition conditions. The surface temperature of the substrate was measured by an infrared thermometer. Changes in the chemical states of the doped silica soot bodies were examined by FT-IR(Fourier-transformed infrared spectroscopy). The deposited particles on the substrate were heated at $1300^{\circ}C$ for 3h in a furnace at a heating rate of 10K/min. Si-O-B bending peak has been found when surface temperature exceeds $720^{\circ}C$. Correspondingly, the case with substrate temperatures above loot produced good consolidation result.

• Korean Journal of Materials Research
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• v.9 no.2
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• pp.144-148
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• 1999

We have studied the deposition characteristics of thick silicon dioxide film on Si substrate by $O_3$/TEOS APCVD(Atmospheric Pressure Chemical Vapor Deposition). The effect of deposition parameters such as the distance between showerhead and substrate, deposition temperature, TEOS flow rate and $O_3$/TEOS ratio on deposition rate, surface morphology, and properties of films as investigated. As deposition temperature increased, deposition rate decreased but the surface morphology and adhesion of film to substrate improved. As the distance between showerhead and substrate decreased, the deposition rate increased. Etching rate using the BOE increased as TEOS flow rate increased, but was independent of$ O_3$/TEOS ratio. Deposition rate of $5\mu\textrm{m}$/hour was obtained under the condition that the distance between showerhead and substrate was 5mm and the deposition temperature was $370^{\circ}C$.

• Journal of Sensor Science and Technology
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• v.14 no.6
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• pp.423-429
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• 2005

In this paper, we proposed the fabrication process of the stable e-beam evaporation and the patterning of metals layer on the polydimethylsiloxane (PDMS) substrate. The metal layer was deposited under the various deposition rate, and its effect to the electrical and mechanical properties (e.g.: adhesion-strength of metal layer) was investigated. The influence of surface roughness to the adhesion-strength was also examined via the tape test. Here, we varied the roughness by changing the reactive ion etching (RIE) duration. The electrode patterning was performed through the conventional photolithography and chemical etching process after e-beam deposition of $200{\AA}$ Ti and $1000{\AA}$ Au. As a result, the adhesion strength of metal layer on the PDMS surface was greatly improved by the oxygen plasma treatment. The e-beam evaporation on the PDMS surface is known to create the wavy topography. Here, we found that such wavy patterns do not effect to the electrical and mechanical properties. In conclusion, the metal patterns with minimum $20{\mu}m$ line width was produced well via the our fabrication process, and its electrical conductance was almost similar to the that of metal patterns on the silicon or glass substrates.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.388-389
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• 2006

Electro-deposition of carbon film on silicon substrate in methanol solution was carried out with various current density, solution temperature and electrode spacing between anode and cathode. The carbon films with smooth surface morphology and high electrical resistance were formed when the distance between electrode was relatively wider. The electrical resistance of the carbon films were independent of both current density and solution temperature.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.81-87
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• 1994

We used IR laser inteferometric technique for measuring the temperature of wafer during cryogenic ECR etching. Using this technique, the effect of RF bias power and microwave power on the wafer temperature during etching period is investigated. As the RF bias power and microwave power was increased, the temperature of the wafer considerably increased and we concluded that to prevent the increase of substrate temperature during etching period, an adequate wafer cooling is needed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.117-124
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• 1996

The .mu.c-Si:H films have been deposited by PeCVD at the various conditions such as hydrogen dilution ratio, substrate temperature and RF power density. Then, we studied their electrical and optical properties. Top gate hydrogenated micro-crystalline silicon thin film transistors($\mu$c-Si:H TFTs) using $\mu$-Si:H and a-SiN:H films have been fabricated by FECVD. The electrical characteristics of the devices have been investigated by semiconductor parameter analyzer and compared with amorphous silicon thin film transistors (a-Si:H TFTs). In this study, on/off current ratio, threshold voltage and the field effect mobility of the $\mu$c-Si:H TFT were $3{\times}10^{4}$, 5.06V and 0.94cm$^{2}$Vs, respectively.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2000.05a
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• pp.743-746
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• 2000

The removal of contaminants of silicon wafers has been investigated by various methods. Laser cleaning is the new dry cleaning technique to replace wafer wet cleaning in the near future. A dry laser cleaning uses inert gas jet to remove contaminant particles lifted off by the action of a KrF excimer laser. A laser cleaning model is developed to simulate the cleaning process and analyze the influence of contaminant particles and experimental parameters on laser cleaning efficiency. The model demonstrates that various types of submicrometer-sized particles from the front sides of silicon wafer can be efficiently removed by laser cleaning. The laser cleaning is explained by a particle adhesion model. including van der Waals forces and hydrogen bonding, and a particle removal model involving rapid thermal expansion of the substrate due to the thermoelastic effect. In addition, the experiment of wafer laser cleaning using KrF excimer laser was conducted to remove various contaminant particles.

• Journal of Information Display
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• v.5 no.2
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• pp.1-5
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• 2004

We developed an a-Si TFT-LCD panel with integrated gate driver circuit using a standard 5-MASK process. To minimize the effect of the a-Si TFT current and LC's capacitance variation with temperature, we developed a new a-Si TFT circuit structure and minimized coupling capacitance by changing vertical architecture above gate driver circuit. Integration of gate driver circuit on glass substrate enables single chip and 3-side free panel structure in a-Si TFT-LCD of QVGA ($240{\times}320$) resolution. And using double ASG structure the dead space of TFT-LCD panel could be further decreased.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.146-146
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• 2010

일반적인 MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor)은 소스와 드레인의 형성을 위해서 불순물을 주입하고 고온의 열처리 과정을 거치게 된다. 이러한 고온의 열처리 과정 때문에 녹는점이 낮은 메탈게이트와 게이트 절연막으로의 high-k 물질의 사용에 제한을 받게된다. 이와 같은 문제점을 보완하기 위해서 소스와 드레인 영역에 불순물 주입공정 대신에 금속접합을 이용한 Schottky Barrier Tunnel Transistor (SBTT)가 제안되었다. SBTT는 $500^{\circ}C$ 이하의 저온에서 불순물 도핑없이 소스와 드레인의 형성이 가능하며 실리콘에 비해서 수십~수백배 낮은 면저항을 가지며, 단채널 효과를 효율적으로 제어할 수 있는 장점이 있다. 또한 고온공정에 치명적인 단점을 가지고 있는 high-k 물질의 적용 또한 가능케한다. 본 연구에서는 p-type SOI (Silicon-On-Insulator) 기판을 이용하여 Pt-silicide 소스와 드레인을 형성하고 전기적인 특성을 분석하였다. 또한 본 연구에서는 기존의 sidewall을 사용하지 않는 새로운 구조를 적용하여 메탈게이트의 사용을 최적화하였고 게이트 절연막으로써 실리콘 옥사이드를 스퍼터링을 이용하여 증착하였기 때문에 저온공정을 성공적으로 수행할 수 있었다. 이러한 게이트 절연막은 열적으로 형성시키지 않고도 70 mv/dec 대의 우수한 subthreshold swing 특성을 보이는 것을 확인하였고, $10^8$정도의 높은 on/off current ratio를 갖는 것을 확인하였다.