• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.268-271
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• 2005

Etch resistance of mask layer on silicon substrate modified by AFM-based Tribo-Nanolithography (TNL) in Aqueous Solution in an aqueous solution was demonstrated. n consists or sequential processes, nano-scratching and wet chemical etching. The simple scratching can form a mask layer on the silicon substrate, which acting as an etching mask. For TNL, a specially designed cantilever with diamond tip, allowing the formation of mask layer on silicon substrate easily by a simple scratching process, has been applied instead of conventional silicon cantilever fur scanning. This study demonstrates how the TNL parameters can affect the etch resistance of mask layer, hence introducing a new process of AFM-based maskless nanolithography in aqueous solution.

• 한국재료학회지
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• 제22권1호
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• pp.8-15
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• 2012

Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

• ETRI Journal
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• 제19권1호
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• pp.26-35
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• 1997

The substrate effects on solid-phase crystallization of amorphous silicon (a-Si) films deposited by low-pressure chemical vapor deposition (LPCVD) using $Si_2H_6$ gas have been extensively investigated. The a-Si films were prepared on various substrates, such as thermally oxidized Si wafer ($SiO_2$/Si), quartz and LPCVD-oxide, and annealed at 600$^{\circ}C$ in an $N_2$ ambient for crystallization. The crystallization behavior was found to be strongly dependent on the substrate even though all the silicon films were deposited in amorphous phase. It was first observed that crystallization in a-Si films deposited on the $SiO_2$/Si starts from the interface between the a-Si and the substrate, so called interface-interface-induced crystallization, while random nucleation process dominates on the other substrates. The different kinetics and mechanism of solid-phase crystallization is attributed to the structural disorderness of a-Si films, which is strongly affected by the surface roughness of the substrates.

• International Journal of Internet, Broadcasting and Communication
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• 제7권2호
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• pp.161-167
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• 2015

The performance of high power LEDs highly depends on the junction temperature. Operating at high junction temperature causes elevation of the overall thermal resistance which causes degradation of light intensity and lifetime. Thus, appropriate thermal management is critical for LED packaging. The main goal of this research is to improve thermal resistance by optimizing and comparing nano-pore silicon-based thermal substrate to insulated metal substrate and direct bonded copper thermal substrate. The thermal resistance of the packages are evaluated using computation fluid dynamic approach for 1 W single chip LED module.

• The Korean Journal of Ceramics
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• 제4권3호
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• pp.222-226
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• 1998

$Cu_3N$ film deposited on silicon oxide substrate by r.f. reactive sputtering technique. Synthesis and properties of copper nitride film were investigated for its possible application to Cu metallization as adhesive interlayer between copper and $SiO_2. Cu_3N$ film was synthesized at the substrate temperature ranging from $100^{\circ}C$ to $200^{\circ}C$ and at nitrogen gas ratio above $X_{N2}=0.4. Cu_3N, CuN_x$, and FGM-structured $Cu/CuN_x$ films prepared in this work passed Scotch-tape test and showed improved adhesion property to silicon oxide substrate compared with Cu film. Electrical resistivity of copper nitride film had a dependency on its lattice constant and was ranged from 10-7 to 10-1 $\Omega$cm. Copper nitride film was, however, unstable when it was annealed at the temperature above $400^{\circ}C$.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권1호
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• pp.17-23
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• 2005

This paper describes the simulation of a micromachined dome-shaped-diaphragm acoustic transducer built on a $1.5{\mu}m$ thick silicon nitride diaphragm ($2,000{\mu}m$ in radius, with a circular clamped boundary on a silicon substrate) with electrodes and piezoelectric ZnO film in a silicon substrate. Finite element analysis with ANSYS 5.6 has been performed to analyze the static and dynamic behaviors of the transducer under both pressure and voltage loadings.

• 전자공학회논문지A
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• 제31A권12호
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• pp.115-121
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• 1994

Aluminum films were chemically vapor deposited for the metallization of the integrated circuits and the spiking characteristics of the direct CVD Al/Si contacts were investigated. When the aluminum was formed by CVD uniform consumption of the substrate silicon was observed, which is quite different from the phenomena observed in sprttered Al. Silicon consumption occured during the deposition of CVD Al and the erosion depth of the silicon was several hundred $\AA$ when the continuous films were formed on the substrate while much less erosion of the silicon occured when the Al were formed in islands. When the submicron contacts were selectively plugged, contact resistances were very low and the erosion depth of the silicon was trivial.

• 한국세라믹학회지
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• 제42권10호
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• pp.645-648
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• 2005

To fabricate a (100) silicon hard master, we used anisotropic wet etching for the embossing. The etching chemical for the sili­con wafer was a TMAH 25$\%$ solution. The anisotropic wet etching produces a smooth sidewall surface inclined at 54.7°, and the surface roughness of the fabricated master is about 1 nm. After spin coating an organic-inorganic sol-gel hybrid resin on a silicon substrate, we used the fabricated master to form patterns on the silicon substrate. Thus, we successfully obtained patterns via the hot embossing technique with the (100) silicon hard master. Moreover, by using a single hydrophobic surface treatment of the master, we succeeded in achieving uniform surface roughness of the embossed patterns for more than ten embossments.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.13-17
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• 1997

It is identified that the diamond films grown o bias-treated (100) silicon showed different surface morphologies and film textures according to the initial applied dc bias voltage at the same growth condition. The highly oriented diamond film (HODF) was successfully grown on -200 V bias-treated silicon substrate in which the heteroepitaxial relation of $(100)_{dimond}//(100)_{si}\; and\; [110]_{diamond}//[110]_{si}$ was identified. On the contrary, the heteroepitaxial relation was considerably disturbed in the samples bias-voltage was a key factor in growing the highly oriented diamond film on (100) silicon substrate. Considering the experimental results, we proposed a new model about heteroepitaxial diamond growth on silicon, in which 9 diamond unit cell are matched with 4 silicon cells and the bond covalency of both atoms is satisfied via the intermediate layer at the interface as well.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.34-36
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• 1997

We have fabricated a patterned diamond field emitter on a silicon substrate. Fine diamond particles were planted on a silicon wafer using conventional scratch method. A silicon oxide film was deposited on the substrate seeded with diamond powder. An array of holes was patterned on the silicon oxide film using VLSI processing technology. Diamond grains were grown using a microwave plasma-assisted chemical vapor deposition. Because diamond could not grow on the silicon oxide barrier, diamond grains filled only the patterned holes in the silicon oxide film, resulting in an array of diamond tips.