• ETRI Journal
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• v.25 no.2
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• pp.73-80
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• 2003

This paper describes an effective method for forming silicon oxide on silica-on-silicon platforms, which results in excellent characteristics for hybrid integration. Among the many processes involved in fabricating silica-on-silicon platforms with planar lightwave circuits (PLCs), the process for forming silicon oxide on an etched silicon substrate is very important for obtaining transparent silica film because it determines the compatibility at the interface between the silicon and the silica film. To investigate the effects of the formation process of the silicon oxide on the characteristics of the silica PLC platform, we compared two silicon oxide formation processes: thermal oxidation and plasma-enhanced chemical vapor deposition (PECVD). Thermal oxidation in fabricating silica platforms generates defects and a cristobalite crystal phase, which results in deterioration of the optical waveguide characteristics. On the other hand, a silica platform with the silicon oxide layer deposited by PECVD has a transparent planar optical waveguide because the crystal growth of the silica has been suppressed. We confirm that the PECVD method is an effective process for silicon oxide formation for a silica platform with excellent characteristics.

• Journal of Sensor Science and Technology
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• v.5 no.1
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• pp.71-77
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• 1996

Considering that polycrystalline silicon, a structural material of the micromachining, is affected by a sacrificial oxide layer, the poly-oxide obtained by the thermal oxidation of polycrystalline silicon is newly proposed and estimated as the sacrificial oxide layer. The grain size of the polycrystalline silicon grown on the poly-oxide is larger than that of poly crystalline silicon grown on the conventional sacrificial oxide layer. As a result of XRD, increase of (111) textures and formation of additional (220) textures are observed on the polycrystaIline silicon deposited on the poly-oxide. Also, the polycrystalline silicon grown on the poly-oxide represents small and uniform stress.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.940-943
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• 2005

The characteristics of a-Si:H TFTs with silicon oxide as passivation layer were reported. It was studied that the insulating characteristics and step coverage characteristics of low temperature silicon oxide before applying to a-Si:H TFT fabrications. With the optimum deposition conditions considering electrical and deposition characteristics, low temperature silicon oxide was applied to a-Si:H TFTs. The changes in characteristics of a-Si:H TFTs were analyzed after replacing silicon nitride passivation layer with low temperature silicon oxide layer. This low temperature silicon oxide can be adapted to high resolution a-Si:H TFT LCD panels.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.10
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• pp.595-600
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• 2016

In this paper, the oxide currents of thin silicon oxides is investigated. The oxide currents associated with the on time of applied voltage were used to measure the distribution of voltage stress induced traps in thin silicon oxide films. The stress induced leakage currents were due to the charging and discharging of traps generated by stress voltage in the silicon oxides. The stress induced leakage current will affect data retention in memory devices. The oxide current for the thickness dependence of stress current and stress induced leakage currents has been measured in oxides with thicknesses between $109{\AA}$, $190{\AA}$, $387{\AA}$, and $818{\AA}$ which have the gate area $10^{-3}cm^2$. The oxide currents will affect data retention and the stress current, stress induced leakage current is used to estimate to fundamental limitations on oxide thicknesses.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• New Physics: Sae Mulli
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• v.68 no.11
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• pp.1203-1207
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• 2018

In this study, silica nanowires were formed using silicon oxide films with different oxygen contents, and their microstructure and physical properties were compared with those of silica nanowires formed using Si wafers. The silicon oxide films were fabricated by using a plasma-enhanced chemical vapor deposition method. Silica nanowires were formed by thermally annealing silicon oxide films coated with nickel films as a catalyst. In the case of silicon oxide films having an oxygen content of approximately 50 at.% or less, the formation mechanism, microstructure, and physical properties of the nanowires were not substantially different from those of the silicon wafer. In particular, the uniformity of the thickness showed better behavior in the silicon oxide films. These results imply that silicon oxide films can be used as an alternative for fabricating high-quality silica nanowires at low cost.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.341-344
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• 2018

In order to achieve a high efficiency for the silicon solar cell, a passivation characteristic that minimizes the electrical loss at a silicon interface is required. In this paper, we evaluated the applicability of the oxide film formed by ozone for the tunnel silicon oxide film. To this end, we fabricated the silicon oxide film by changing the condition of ozone oxidation and compared the characteristics with the oxide film formed by the existing nitric acid solution. The ozone oxidation was formed in the temperature range of $300{\sim}500^{\circ}C$ at an ozone concentration of 17.5 wt%, and the passivation characteristics were compared. Compared to the silicon oxide film formed by nitric acid oxidation, implied open circuit voltage (iVoc) was improved by ~20 mV in the ozone oxidation and the ozone oxidation after the nitric acid pretreatment was improved by ~30 mV.

• Journal of the Semiconductor & Display Technology
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• v.2 no.1
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• pp.21-24
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• 2003

Sludged silicon powders that are generated during silicon ingot slicing process have potential usage as silicon source in fabricating silicon carbide powders by adding carbon. A thermodynamic calculation is performed to consider a plausible formation condition for the silicon carbide powders. A thin silicon oxide layer around silicon powder is sufficient to supply equilibrium oxygen partial pressure at the formation temperature($1400^{\circ}C$) of the silicon carbide in the Si-C-O ternary system. Formation of silicon carbide by using the sludged silicon powders is more efficient than by using silicon oxide powders.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.6
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• pp.412-417
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• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.235-238
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• 1999

Silicon dioxide films were prepared by anodizing silicon wafers in an ethylene $glycol+HNO_3(0.04{\;}N)$ at 20 to $70^{\circ}C$. The voltage between silicon anode and platinum cathode was measured during this process. Under the constant current electrolysis, the voltage increased with oxide film growth. The transition time at which the voltage reached the predetermined value depended on the temperature of the electrolyte. After the time of electrolysis reached the transition time, the anodization was changed the constant voltage mode. The depth profile of oxide film/Si substrate was confirmed by XPS analysis to study the influence of the electrolyte temperature on the anodization. Usually, the oxide-silicon peaks disappear in the silicon substrate, however, this peak was not small at $45^{\circ}C$ in this region.