• Transactions of Materials Processing
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• v.14 no.5 s.77
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• pp.432-438
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• 2005

Among the most of manufacturing process, plastic deformation method offers a significant advantage in productivity and enable mass production with controlled quality and low cost. From the point of view, micro forming is a well suited technology in manufacturing very small metallic parts, in particular for mass production, as they are required in many industrial products. Meanwhile, Al 5083 superplastic alloy with very small grains has a great advantage in achieving micro deformation under low stress due to its relatively low strength at a specific high temperature range. This paper describes the micro formability of Al 5083 superplastic alloy and its application to die forging of micro patterns. Micro formability tests of Al 5083 superplastic alloy were carried out with the specially designed micro forging system by using V-grooved micro dies and pyramidal dies made of (100) silicon. With these dies, micro forging was conducted by varying the applied load, material temperature and forging time The micro formability of Al 5083 superplastic alloy was evaluated by comparing $R_f$ value, where $R_f\;=\;A_f/A_v$ ($A_v$ : cross-sectional area of the flowed metal, $A_v$ : cross sectional area of V-groove). The micro formability of 3 dimensional Patterns was also evaluated using Pyramidal type micro dies.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.47-52
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• 2013

Gold wire has long been used as a proven method of connecting a silicon die to a substrate in wide variety of package types, delivering high yield and productivity. However, with the high price of gold, the semiconductor packaging industry has been implementing an alternate wire material. These materials may include silver (Ag) or copper (Cu) alloys as an alternative to save material cost and maintain electrical performance. This paper will analyze and compare the electrical characteristics of several wire types. For the study, typical 0.6 mil, 0.8 mil and 1.0 mil diameter wires were selected from various alloy types (2N gold, Palladium (Pd) coated/doped copper, 88% and 96% silver) as well as respective pure metallic wires for comparison. Each wire model was validated by comparing it to electromagnetic simulation results and measurement data. Measurements from the implemented test boards were done using a vector network analyzer (VNA) and probe station setup. The test board layout consisted of three parts: 1. Analysis of the diameter, length and material characteristic of each wire; 2. Comparison between a microstrip line and the wire to microstrip line transition; and 3. Analysis of the wire's cross-talk. These areas will be discussed in detail along with all the extracted results from each type the wire.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.52-59
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• 2010

This paper proposes a high-resolution and high-frame rate CMOS image sensor with column-wise cyclic ADC. The proposed ADC uses the sharing techniques of OTAs and capacitors for low-power consumption and small silicon area. The proposed ADC was verified implementing the prototype chip as QVGA image sensor. The measured maximum frame rate is 120 fps, and the power consumption is 130 mW. The power supply is 3.3 V, and the die size is $4.8\;mm\;{\times}\;3.5\;mm$. The prototype chip was fabricated in a 2-poly 3-metal $0.35-{\mu}m$ CMOS process.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.4
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• pp.39-45
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• 2015

In this paper, variable rate CDR(Clock and Data Recovery) circuit adopting blind oversampling architecture is presented. The clock recovery circuit is implemented by using wide range voltage controlled oscillator and band selection method and the data recovery circuit is designed to digital circuit used majority voting method in order to low power and small area. The designed low power variable clock and data recovery is implemented by wide range voltage controlled oscillator and digital data recovery circuit. The designed variable rate CDR is operated from 10 bps to 2 Mbps. The total power consumption is about 4.4mW at 1MHz clock. The supply voltage is 1.2V. The designed die area is $120{\mu}m{\times}75{\mu}m$ and this circuit is fabricated in $0.13{\mu}m$ CMOS process.

• Design & Manufacturing
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• v.16 no.3
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• pp.58-65
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• 2022

Micro-fluidic chip has been fabricated by lithography process on silicon or glass wafer, casting using PDMS, injection molding of thermoplastics or 3D printing, etc. Among these processes, 3D printing can fabricate micro-fluidic chip directly from the design without master or template for fluidic channel fabricated previously. Due to this direct printing, 3D printing provides very fast and economical method for prototyping micro-fluidic chip comparing to conventional fabrication process such as lithography, PDMS casting or injection molding. Although 3D printing is now used more extensively due to this fast and cheap process done automatically by single printing machine, there are some issues on accuracy or surface characteristics, etc. The accuracy of the shape and size of the micro-channel is limited by the resolution of the printing and printing direction or layering direction in case of SLM type of 3D printing using UV curable resin. In this study, the printing direction and thickness of each printing layer are investigated to see the effect on the size, shape and surface of the micro-channel. A set of micro-channels with different size was designed and arrayed orthogonal. Micro-fluidic chips are 3D printed in different directions to the micro-channel, orthogonal, parallel, or skewed. The shape of the cross-section of the micro-channel and the surface of the micro-channel are photographed using optical microscopy. From a series of experiments, an optimal printing direction and process conditions are investigated for 3D printing of micro-fluidic chip.

• Journal of Technologic Dentistry
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• v.45 no.1
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• pp.1-7
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• 2023

Purpose: To evaluate the marginal and internal fit of metal coping fabricated by a metal three-dimensional (3D) printer that uses selective laser melting (SLM). Methods: An extraoral scanner was used to scan a die of the prepared maxillary right first molar, and the coping was designed using computer-aided design software and saved as an stereo lithography (STL) file. Ten specimens were printed with an SLM-type metal 3D printer (SLM group), and 10 more specimens were fabricated by casting the castable patterns output generated by a digital light processing-type resin 3D printer (casting the 3D printed resin patterns [CRP] group). The fit was measured using the silicon replica technique, and 8 points (A to H) were set per specimen to measure the marginal (points A, H) and internal (points B~G) gaps. The differences among the groups were compared using the Mann-Whitney U-test (α=0.05). Results: The mean of marginal fit in the SLM group was 69.67±18.04 ㎛, while in the CRP group was 117.10±41.95 ㎛. The internal fit of the SLM group was 95.18±41.20 ㎛, and that of the CRP group was 86.35±32 ㎛. As a result of statistical analysis, there was a significant difference in marginal fit between the SLM and CRP groups (p<0.05); however, there was no significant difference in internal fit between the SLM group and the CRP group (p>0.05). Conclusion: The marginal and internal fit of SLM is within the clinically acceptable range, and it seems to be applicable in terms of fit.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of Dental Rehabilitation and Applied Science
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• v.25 no.2
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• pp.95-107
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• 2009

The purpose of this research was to examine the fitness of zirconia cores that were made by different sintering methods; generic electricity furnace and microwave furnace. Firstly, 12 cores for each group were made by using each different sintering process and attached them to a metal die with silicon. The internal and marginal gap of sintered zirconia was measured by using Skyscan 1076 micro-CT, then it was reorganized by CT-An software. To each samples, we extracted B-L image, M-D image of cutting side, and cross-sectional side of tooth long axis and calculated the mean value of marginal, axial, and occlusal gap each side. Results: 1. The mean marginal gap of sintered zirconia was $36.20{\mu}m$ for EVE, $47.67{\mu}m$ for LAV, $52.47{\mu}m$ for DEN, and $54.63{\mu}m$ for CER. 2. For the axial wall, the research showed the largest value of $63.49{\mu}m$ for EVE, but there were no statistical significance. 3. In related to the occlusal internal measurement, DEN showed the smallest value ($77.06{\mu}m$), EVE and CER showed significantly high value. From this study, it is suggested that CAD/CAM zirconia core which was made in the process of microwave sintering has clinically acceptable values in marginal and internal gap.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.98-106
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• 2009

This work proposes a 1280-RGB $\times$ 800-Dot 70.78mW 0.l3um CMOS LCD driver IC (LDI) for high-performance 16M-color low temperature poly silicon (LTPS) thin film transistor liquid crystal display (TFT-LCD) systems such as ultra mobile PC (UMPC) and mobile applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed LDI optimizes power consumption and chip area at high resolution based on a resistor-string based architecture. The single column driver employing a 1:12 MUX architecture drives 12 channels simultaneously to minimize chip area. The implemented class-AB amplifier achieves a rail-to-rail operation with high gain and low power while minimizing the effect of offset and output deviations for high definition. The supply- and temperature-insensitive current reference is implemented on chip with a small number of MOS transistors. A slew enhancement technique applicable to next-generation source drivers, not implemented on this prototype chip, is proposed to reduce power consumption further. The prototype LDI implemented in a 0.13um CMOS technology demonstrates a measured settling time of source driver amplifiers within 1.016us and 1.072us during high-to-low and low-to-high transitions, respectively. The output voltage of source drivers shows a maximum deviation of 11mV. The LDI with an active die area of $12,203um{\times}1500um$ consumes 70.78mW at 1.5V/5.5V.