• 한국세라믹학회지
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• 제46권5호
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• pp.510-514
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• 2009

The microstructure and mechanical behavior of deformed silicon were characterized using transmission electron microscopy and nanoindentation. Structural defects such as stacking faults and dislocations were observed through the diffraction contrast in transmission electron microscopy. The mechanical properties of deformed Si and 111 Si wafer and mechanical behaviors during contact loading were also characterized using nanoindentation. The hardness values of silicon samples were ${\sim}10$ GPa and the elastic modulus were varied with indentation conditions. Elbow or pop-out behaviors were found in load-displacement curves of silicon samples during nanoindentation. Deformed silicon showed 'pop-out' behavior more frequently under the load of 10 mN, which is attributed to the structural defects in deformed silicon.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권2호
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• pp.164-169
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• 2008

The effects of the antisite related defects on the electronic structure of silica and the gate leakage current have been investigated using first-principles calculations. Energy levels related to the antisite defects in silicon dioxide have been introduced into the bandgap, which are nearly 2.0 eV from the top of the valence band. Combining with the electronic structures calculated from first-principles simulations, tunneling currents through the silica layer with antisite defects have been calculated. The tunneling current calculations show that the hole tunneling currents assisted by the antisite defects will be dominant at low oxide field whereas the electron direct tunneling current will be dominant at high oxide field. With increased thickness of the defect layer, the threshold point where the hole tunneling current assisted by antisite defects in silica is equal to the electron direct tunneling current extends to higher oxide field.

• 한국결정성장학회지
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• 제16권2호
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• pp.66-70
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• 2006

실리콘웨이퍼 표면에 기계적인 손상을 가한 후 산화 열처리 공정을 실시하면 온도와 기계적인 손상의 크기에 따라 여러 가지 결정 결함이 발생된다. 기계적인 손상이 크고 열처리 온도가 증가함에 따라 dislocation loop 등의 대형 결함들이 발생되고 열처리 온도가 낮거나 손상의 크기가 작을수록 OISF(Oxidation Induced Stacking Faults)등의 소형 결함들이 많이 발생된다. Minority carrier lifetime을 측정하여본 결과 결함의 크기가 작을수록 minority carrier lifetime이 높은 것으로 밝혀졌다. 더욱이 dislocation loop 등의 결정 결함보다는 결함 발생 이전 단계인 strained layer등이 금속불순물에 대한 gettering의 효과가 더욱 높음을 알 수 있었다.

• 한국결정성장학회지
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• 제6권1호
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• pp.11-18
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• 1996

Czochralski법으로 성장된 대구경(8인치 이상) 규소 단결정속에 폰재하는 결정 결 함을 규명하였다. Ring형 산화 적충 결함(Oxidation Induced Stacking Faults, 일명 OISF)의 발생 형태를 조사하였다. Minority life time을 mappmg하여 본 결과, rmg형 OISF의 폰재는 재료의 전기적 성질에 영향을 미칠 가능성이 높은 것으로 확인되었다. OISF의 핵 생성에 미치는 냉각 속도의 영향을 조사한 결과 homogeneous적 핵 생성 및 성장 현상을 확인할 수 있었다. 또한 COP(Crystal Originated Particle)의 주원인인 FPD(Flow Pattern Defects)의 발생은 용 체의 응고 속도에 크게 화우됨을 발견하였다. 이들 결함의 상반된 발생 현상의 제어를 위하여 는 인상 속도는 느리게, 또한 $950^{\circ}C$ 근처에서의 냉각속도는 빠르게 하는 것이 바람직한 것으로 결함 발생 제어 모델이 제시되었다.

• 한국결정성장학회지
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• 제24권5호
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• pp.190-195
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• 2014

방향성 응고법으로 잉곳을 성장시킬 때 발생하는 온도 구배에 의해 잉곳 내에 결함이 생성되고 잔류 응력이 남게 된다. 이 결함과 잔류 응력은 잉곳의 성장 조건에 따라 달라지며, 웨이퍼의 특성에 큰 영향을 미칠 수 있다. 성장 속도의 변화에 상관 없이 대부분의 잉곳에서는 하부 영역에 비해 상부 영역에서 결정립과 쌍정경계의 크기가 작았으며, 결정립계뿐만 아니라 결정립 내에도 전위 밀도가 높았다. 이것은 상부 영역에서 성장 중에 받는 열 응력이 하부 영역보다 크다는 것을 암시한다. 두 잉곳 간의 차이를 보았을 때에는 성장 속도가 느린 잉곳에서 전위 밀도가 감소하였으며, 웨이퍼의 평탄도, 뒤틀림, 휨, 절단자국이 낮게 측정되었다. 따라서 다결정 성장 공정에서는 냉각 속도가 결함이나 잔류 응력의 발생에 미치는 영향이 크며, 그로 인하여 웨이퍼의 특성이 달라지는 것을 알 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제5권4호
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• pp.143-147
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• 2004

Surface defects and bulk defects on SOI wafers are studied. Two new metrologies have been proposed to characterize surface and bulk defects in epitaxial layer transfer (ELTRAN) wafers. They included the following: i) laser scattering particle counter and coordinated atomic force microscopy (AFM) and Cu-decoration for defect isolation and ii) cross-sectional transmission electron microscope (TEM) foil preparation using focused ion beam (FIB) and TEM investigation for defect morphology observation. The size of defect is 7.29 urn by AFM analysis, the density of defect is 0.36 /cm$^2$ at as-direct surface oxide defect (DSOD), 2.52 /cm$^2$ at ox-DSOD. A hole was formed locally without either the silicon or the buried oxide layer (Square Defect) in surface defect. Most of surface defects in ELTRAN wafers originate from particle on the porous silicon.

• 한국결정성장학회지
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• 제20권2호
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• pp.101-105
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• 2010

플라즈마 에쳐 내에 사용되는 실리콘 전극과 링 부품은 사용 중에 강한 플라즈마와 접촉하면서 주기적인 가열과 냉각 과정을 거친다. 이 때 부품의 표면에서는 열 응력으로 인하여 PSB라고 하는 띠 형상의 결함이 생성되며 이로 인하여 그 수명을 다하게 된다. 원료인 실리콘 잉곳의 관점에서 그 수명에 미치는 인자를 살펴보았다. 잉곳의 등급, 즉 S/F와 S/A에 따라 불순물과 결함의 농도를 GDMS와 ${\mu}$-PCD로 평가하여 잉곳의 어떤 요소들에 의하여 수명이 결정되는가를 분석하였다. 그 결과, {001} 면상에서 관찰되는 <110> 방향의 면 결함들이 PSB와 연결될 가능성이 있음을 제안하였다.

• 한국결정성장학회지
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• 제25권1호
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• pp.13-19
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• 2015

Among the various possible factors affecting the Minority Carrier Life Time (MCLT) of the mc-Si crystal, dislocations formed during the cooling period after solidification were found to be a major element. It was confirmed that other defects such as grain boundary or twin boundary were not determinative defects affecting the MCLT because most of these defects seemed to be formed during the solidification period. With a measurement of total thickness variation (TTV) and bow of the silicon wafers, it was found that residual stress remaining in the mc-Si crystal might be another major factor affecting the MCLT. Thus, it is expected that better quality of mc-Si can be grown when the cooling process right after solidification is carried out as slow as possible.

• 한국재료학회지
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• 제22권1호
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• pp.8-15
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• 2012

Silicon-based thin film was prepared at room temperature by an electrochemical deposition method and a feasibility study was conducted for its use as an anode material in a rechargeable lithium battery. The growth of the electrodeposits was mainly concentrated on the surface defects of the Cu substrate while that growth was trivial on the defect-free surface region. Intentional formation of random defects on the substrate by chemical etching led to uniform formation of deposits throughout the surface. The morphology of the electrodeposits reflected first the roughened surface of the substrate, but it became flattened as the deposition time increased, due primarily to the concentration of reduction current on the convex region of the deposits. The electrodeposits proved to be amorphous and to contain chlorine and carbon, together with silicon, indicating that the electrolyte is captured in the deposits during the fabrication process. The silicon in the deposits readily reacted with lithium, but thick deposits resulted in significant reaction overvoltage. The charge efficiency of oxidation (lithiation) to reduction (delithiation) was higher in the relatively thick deposit. This abnormal behavior needs to clarified in view of the thickness dependence of the internal residual stress and the relaxation tendency of the reaction-induced stress due to the porous structure of the deposits and the deposit components other than silicon.

• 한국세라믹학회지
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• 제32권12호
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• pp.1377-1382
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• 1995

A high-resolution transmission electron microscopy study on the lattice defects formed in the high energy P ion implanted silicon was carried out on an atomic level. Results show that Lomer dislocations, 60$^{\circ}$perfect dislocations, 60$^{\circ}$ dislocation dipole and extrinsic stacking fault formed in the near Rp of as-implanted specimen. In the annelaed specimens, interstitial Frank loops, 60$^{\circ}$perfect disolations, 60$^{\circ}$dislocation dipoles, stacking faults, precipitates, perfect dislocation loops and <112> rodlike defects existed exclusively near in the Rp with various annealing temperature and time. From these results, it is concluded that extended secondary defects as well as the point defect clusters could be formed without annealing. Even at low temperature annealing such as 55$0^{\circ}C$, small interstitial Frank loops could be formed and precipitates were also formed by $700^{\circ}C$ annealing. The defect band annealed at 100$0^{\circ}C$ for 1 hr could be divided into two regions depending on the distribution of the secondary defects.