• Title/Summary/Keyword: silicide

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Investigation of $WSi_2$ Gate for the Integration With $HfO_3$gate oxide for MOS Devices (MOS 소자를 위한 $HfO_3$게이트 절연체와 $WSi_2$게이트의 집적화 연구)

  • 노관종;양성우;강혁수;노용한
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.832-835
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    • 2001
  • We report the structural and electrical properties of hafnium oxide (HfO$_2$) films with tungsten silicide (WSi$_2$) metal gate. In this study, HfO$_2$thin films were fabricated by oxidation of sputtered Hf metal films on Si, and WSi$_2$was deposited directly on HfO$_2$by LPCVD. The hysteresis windows in C-V curves of the WSi$_2$HfO$_2$/Si MOS capacitors were negligible (<20 mV), and had no dependence on frequency from 10 kHz to 1 MHz and bias ramp rate from 10 mV to 1 V. In addition, leakage current was very low in the range of 10$^{-9}$ ~10$^{-10}$ A to ~ 1 V, which was due to the formation of interfacial hafnium silicate layer between HfO$_2$and Si. After PMA (post metallization annealing) of the WSi$_2$/HfO$_2$/Si MOS capacitors at 500 $^{\circ}C$ EOT (equivalent oxide thickness) was reduced from 26 to 22 $\AA$ and the leakage current was reduced by approximately one order as compared to that measured before annealing. These results indicate that the effect of fluorine diffusion is negligible and annealing minimizes the etching damage.

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Low resistivity Ohmic Co/Si/Co contacts to n-type 4H-SiC (낮은 접촉 저항을 갖는 Co/Si/co n형 4H-SiC의 오옴성 접합)

  • Kim, C.K.;Yang, S.J.;Lee, J.H.;Cho, N.I.;Jung, K.H.;Kim, N.K.;Kim, E.D.;Kim, D.H.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07b
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    • pp.764-768
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    • 2002
  • Characteristics of ohmic Co/Si/Co contacts to n-type 4H-SiC are investigated systematically. The ohmic contacts were formed by annealing Co/Si/Co sputtered sequentially. The annealings were performed at $800^{\circ}C$ using RTP in vacuum ambient and $Ar:H_2$(9:1) ambient, respectively. The specific contact resistivity$(\rho_c)$, sheet resistance$(R_s)$, contact resistance$(R_c)$, transfer length$(L_T)$ were calculated from resistance$(R_T)$ versus contact spacing(d) measurements obtained from TLM(transmission line method) structure. While the resulting measurement values of sample annealed at vacuum ambient were $\rho_c=1.0{\tiimes}10^{-5}{\Omega}cm^2$, $R_c=20{\Omega}$ and $L_T$ = 6.0 those of sample annealed at $Ar:H_2$(9:1) ambient were $\rho_c=4.0{\tiimes}10^{-6}{\Omega}cm^2$, $R_c=4.0{\Omega}$ and $L_T$ = 2.0. The physical properties of contacts were examined using XRD and AES. The results showed that cobalt silicide was formed on SiC and Co was migrated into SiC.

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The Research of Ni/Cu/Ag Contact Solar Cells for Low Cost & High Efficiency in Crystalline Solar Cells (결정질 실리콘 태양전지의 저가 고 효율화를 위한 Ni/Cu/Ag 전극 태양전지)

  • Cho, Kyeong-Yeon;Lee, Ji-Hun;Lee, Soo-Hong
    • 한국태양에너지학회:학술대회논문집
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    • 2009.04a
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    • pp.214-219
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    • 2009
  • In high-efficiency crystalline silicon solar cells, If high-efficiency solar cells are to be commercialized. It is need to develop superior contact formation method and material that can be inexpensive and simple without degradation of the solar cells ability. For reason of plated metallic contact is not only high metallic purity but also inexpensive manufacture. It is available to apply mass production. Especially, Nickel, Copper and Silver are applied widely in various electronic manufactures as easily formation is available by plating. The metallic contact system of silicon solar cell must have several properties, such as low contact resistance, easy application and good adhesion. Ni is shown to be a suitable barrier to Cu diffusion as well as desirable contact metal to silicon. Nickel monosilicide(NiSi) has been suggested as a suitable silicide due to its lower resistivity, lower sintering temperature and lower layer stress than $TiSi_2$. Copper and Silver can be plated by electro & light-induced plating method. Light-induced plating makes use the photovoltaic effect of solar cell to deposite the metal on the front contact. The cell is immersed into the electrolytic plating bath and irradiated at the front side by light source, which leads to a current density in the front side grid. Electroless plated Ni/ Electro&light-induced plated Cu/ Light-induced plated Ag contact solar cells result in an energy conversion efficiency of 14.68 % on $0.2{\sim}0.6{\Omega}{\cdot}cm,\;20{\times}20mm^2$, CZ(Czochralski) wafer.

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Investigation of the Ni/Cu metal grid space for high-effiency, low cost crystlline silicon solar cells (고효율, 저가화 태양전지에 적합한 Ni/Cu 금속 전극 간격에 따른 특성 평가)

  • Kim, Min-Jeong;Lee, Ji-Hun;Cho, Kyeng-Yeon;Lee, Soo-Hong
    • 한국태양에너지학회:학술대회논문집
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    • 2009.04a
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    • pp.225-229
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    • 2009
  • The front metal contact is one of the most important element influences in efficiency in the silicon solar cell. First of all selective of the material and formation method is important in metal contacts. Commercial solar cells with screen-printed contacts formed by using Ag paste process is simple relatively and mass production is easy. But it suffer from a low fill factor and a high shading loss because of high contact resistance. Besides Ag paste too expensive. because of depends income. This paper applied for Ni/Cu metallization replace for paste of screen printing front metal contact. Low cost Ni and Cu metal contacts have been formed by using electroless plating and electroplating techniques to replace the screen-printed Ag contacts. Ni has been proposed as a suitable silicide for the salicidation process and is expected to replace conventional silicides. Copper is a promising material for the electrical contacts in solar cells in terms of conductivity and cost. In experiments Ni/Cu metal contact applied same grid formation of screen-printed solar cell. And it has variation of different grid spacing. It was verified that the wide spacing of grid finger could increase the series resistance also the narrow spacing of grid finger also implies a grid with a higher density of grid fingers. Through different grid spacing found alteration of efficiency.

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Formation of Nickel Silicide from Atomic Layer Deposited Ni film with Ti Capping layer

  • Yun, Sang-Won;Lee, U-Yeong;Yang, Chung-Mo;Na, Gyeong-Il;Jo, Hyeon-Ik;Ha, Jong-Bong;Seo, Hwa-Il;Lee, Jeong-Hui
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2007.06a
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    • pp.193-198
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    • 2007
  • The NiSi is very promising candidate for the metallization in 60nm CMOS process such as FUSI(fully silicided) gate and source/drain contact because it exhibits non-size dependent resistance, low silicon consumption and mid-gap workfunction. Ni film was first deposited by using ALD (atomic layer deposition) technique with Bis-Ni precursor and $H_2$ reactant gas at $220^{\circ}C$ with deposition rate of $1.25{\AA}/cycle$. The as-deposited Ni film exhibited a sheet resistance of $5{\Omega}/{\square}$. RTP (repaid thermal process) was then performed by varying temperature from $400^{\circ}C$ to $900^{\circ}C$ in $N_2$ ambient for the formation of NiSi. The process window temperature for the formation of low-resistance NiSi was estimated from $600^{\circ}C$ to $800^{\circ}C$ and from $700^{\circ}C$ to $800^{\circ}C$ with and without Ti capping layer. The respective sheet resistance of the films was changed to $2.5{\Omega}/{\square}$ and $3{\Omega}/{\square}$ after silicidation. This is because Ti capping layer increases reaction between Ni and Si and suppresses the oxidation and impurity incorporation into Ni film during silicidation process. The NiSi films were treated by additional thermal stress in a resistively heated furnace for test of thermal stability, showing that the film heat-treated at $800^{\circ}C$ was more stable than that at $700^{\circ}C$ due to better crystallinity.

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Deposition and Characterization of $HfO_2/SiNx$ Stack-Gate Dielectrics Using MOCVD (MOCVD를 이용한 $HfO_2/SiNx$ 게이트 절연막의 증착 및 물성)

  • Lee Taeho;Oh Jaemin;Ahn Jinho
    • Journal of the Microelectronics and Packaging Society
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    • v.11 no.2 s.31
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    • pp.29-35
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    • 2004
  • Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

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Phase Distribution and Interface Chemistry by Solid State SiC/Ni Reaction

  • Lim, Chang-Sung;Shim, Kwang-Bo;Shin, Dong-Woo;Auh, Keun-Ho
    • The Korean Journal of Ceramics
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    • v.2 no.1
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    • pp.19-24
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    • 1996
  • The phase distribution and interface chemistry by the solid-state reaction between SiC and nickel were studied at temperatures between $550 \;and\; 1250^{\circ}C$ for 0.5-100 h. The reaction with the formation of silicides and carbon was first observed above $650^{\circ}C$. At $750^{\circ}C$, as the reaction proceeded, the initially, formed $Ni_3Si_2$ layer was converted to $Ni_2$Si. The thin nickel film reacted completely with SiC after annealing at $950^{\circ}C$ for 2 h. The thermodynamically stable $Ni_2$Si is the only obsrved silicide in the reaction zone up to $1050^{\circ}C$. The formation of $Ni_2$Si layers with carbon precipitates alternated periodically with the carbon free layers. At temperatures between $950^{\circ}C$ and $1050^{\circ}C$, the typical layer sequences in the reaction zone is determined by quantitative microanalysis to be $SiC/Ni_2$$Si+C/Ni_2$$Si/Ni_2$$Si+C/…Ni_2$Si/Ni(Si)/Ni. The mechanism of the periodic band structure formation with the carbon precipitation behaviour was discussed in terms of reaction kinetics and thermodynamic considerations. The reaction kinetics is proposed to estimate the effective reaction constant from the parabolic growth of the reaction zone.

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Metal Gate Electrode in SiC MOSFET (SiC MOSFET 소자에서 금속 게이트 전극의 이용)

  • Bahng, W.;Song, G.H.;Kim, N.K.;Kim, S.C.;Seo, K.S.;Kim, H.W.;Kim, E.D.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07a
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    • pp.358-361
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    • 2002
  • Self-aligned MOSFETS using a polysilicon gate are widely fabricated in silicon technology. The polysilicon layer acts as a mask for the source and drain implants and does as gate electrode in the final product. However, the usage of polysilicon gate as a self-aligned mask is restricted in fabricating SiC MOSFETS since the following processes such as dopant activation, ohmic contacts are done at the very high temperature to attack the stability of the polysilicon layer. A metal instead of polysilicon can be used as a gate material and even can be used for ohmic contact to source region of SiC MOSFETS, which may reduce the number of the fabrication processes. Co-formation process of metal-source/drain ohmic contact and gate has been examined in the 4H-SiC based vertical power MOSFET At low bias region (<20V), increment of leakage current after RTA was detected. However, the amount of leakage current increment was less than a few tens of ph. The interface trap densities calculated from high-low frequency C-V curves do not show any difference between w/ RTA and w/o RTA. From the C-V characteristic curves, equivalent oxide thickness was calculated. The calculated thickness was 55 and 62nm for w/o RTA and w/ RTA, respectively. During the annealing, oxidation and silicidation of Ni can be occurred. Even though refractory nature of Ni, 950$^{\circ}C$ is high enough to oxidize it. Ni reacts with silicon and oxygen from SiO$_2$ 1ayer and form Ni-silicide and Ni-oxide, respectively. These extra layers result in the change of capacitance of whole oxide layer and the leakage current

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A Study on the Properties of WS $i_{x}$ Thin Film with Formation Conditions of Polycide (폴리사이드 형성 조건에 따른 WS $i_{x}$ 박막 특성에 관한 연구)

  • 정양희;강성준;김경원
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.52 no.9
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    • pp.371-377
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    • 2003
  • We perform the physical analysis such that Si/W composition ratios and phosphorus distribution change in the W/S $i_{x}$ thin films according to phosphorus concentration of polysilicon and W $F_{6}$ flow rate for the formation of WS $i_{x}$ polycide used as a gate electrode. We report that these physical characteristics have effects on the contact resistance between word line and bit line in DRAM devices. RBS measurements show that for the samples having phosphorus concentrations of 4.75 and 6.0${\times}$10$^{2-}$ atoms/㎤ in polysilicon, by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, Si/W composition ratio has increases to 2.05∼2.24 and 2.01∼2.19, respectively. SIMS analysis give that phosphorus concentration of polysilicon for both samples have decreases after annealing, but phosphorus concentration of WS $i_{x}$ thin film has increases by applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm. The contact resistance between word line and bit line in the sample with phosphorus concentration of 6.0 ${\times}$ 10$^{20}$ atoms/㎤ in polysilicon is lower than the sample with 4.75 ${\times}$ 10$^{20}$ atoms/㎤ After applying W $F_{6}$ flow rates decreases from 4.5 to 3.5 sccm, the contact resistance has been improved dramatically from 10.1 to 2.3 $\mu$ $\Omega$-$\textrm{cm}^2$.

Preparation and Characterization of Heating Element for Inkjet Printer (잉크젯 프린터용 발열체의 제작과 특성연구)

  • 장호정;노영규
    • Journal of the Microelectronics and Packaging Society
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    • v.10 no.3
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    • pp.1-7
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    • 2003
  • The crystallized stable cobalt silicide$(CoSi_2)$ films were prepared on $poly-Si/SiO_2/Si$substrates for the application of inkjet printing head as a heating element with omega shape. The structural images and temperature resistance coefficient were investigated. The value of temperature resistance coefficient of the heating element was found to be about $0.0014/^{\circ}C$. The maximum power of the heating element was 2 W at the applied voltage of 2 V, 10 kHz in frequency and $1{\mu}s$ in pulse width. From the investigation of fatigue property according to the repeated applied voltages, there was no drastic changes in the resistances of heating element under the condition of $10^8$ pulsed cycles at below 15 V biased voltage. In contrast, the resistance of heating element was greatly increased at $10^6$ pulsed cycles when the heating element was operated at 17 V.

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