• Journal of Institute of Control, Robotics and Systems
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• v.5 no.4
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• pp.481-488
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• 1999

A thermal model based on the chamber geometry of the industry-standard AST SHS200MA rapid thermal processing system has been developed for the study of thermal uniformity and process repeatability thermal model combines radiation energy transfer directly from the tungsten-halogen lamps and the steady-state thermal conducting equations. Because of the difficulties of solving partial differential equation, calculation of wafer temperature was performed by using finite-difference approximation. The proposed thermal model was verified via titanium silicidation experiments. As a result, we can conclude that the thermal model show good estimation of wafer surface temperature distribution.

• 전자공학회논문지 IE
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• v.44 no.3
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• pp.1-5
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• 2007

A new field emission tip array was realized by Ti silicidation of Ti coated Si tip, which has long term durability, chemical stability, and high emission current density. The fabricated Ti silicided FE tip array under high vacuum condition of about $10^{-8}Torr$ shows that the turn-on voltage is about 40V and the emission current is about $69{\mu}A$ when the bias of 150V is applied between anode and cathode of $100{\mu}m$ distance.

• Journal of the Korean Vacuum Society
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• v.4 no.1
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• pp.91-103
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• 1995

SF6 플라즈마를 이용한 텅스템 실리사이드 식각공정에서 전력, 압력, 전극간 거리, 기판온도 등의 공정변수와 CI2 첨가 기체가 식각율, 이방성, RIE Lag 등의 식각특성에 미치는 영향을 살펴보았다. 입력 전력이 증가할수록 식각율이 증가하였고 RIE Lag는 감소하였다. 식각율은 150mtorr에서 최대가 되었는데 이는 이온과 반응성 라디칼의 공동작용효과가 가장 크게 나타나기 때문으로 생각된다. 또한 압력이 작아질수록 이온의 에너지가 증가하고 이온의 분산현상이 감소하여 RIE Lag이 감소되었다. 전극간 거리가 감소할수록 식각율은 증가하고 RIE Lag은 감소되었으나 이방성은 악화되는 것으로 나타났다. 기판 온도가 증가할수록 표면 반응이 활발해져 총 식각율은 증가하였으며 반응성 라디칼의 도랑 내부로의 확산이 용이하게 이루어져 RIE Lag가 감소하였으나 화학적 식각의 증가로 이방성은 악화되었다. 염소의 첨가량이 증가할수록 도랑 벽면에 보호막이 형성되어 식각율 및 RIE Lag은 감소하였으며 이방성은 향상되는 것으로 나타났다.

• Proceedings of the Korean Vacuum Society Conference
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• 1997.07a
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• pp.34-34
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• 1997

• Korean Journal of Materials Research
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• v.8 no.1
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• pp.10-12
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• 1998

Si FEA 로부터 tip의 표면을 Ti금속으로 silicidation한 새로운 2극형 Ti-실리사이드 FEA를 제작하고 이의 전계방출 특성을 Si FEA의 경우와 비교하였다. 양극과 음극간의 거리를 10$\mu\textrm{m}$로 유지하고 $10^{-8}$Torr의 고진공 상태에서 측정한 실리사이드 FEA의 turn-on전압은 약 40V로, 전계방출전류와 정상상태 전류 변동율은 150V의 바이어스 아래에서 약 3x$10^{-2}$ $\mu$A/tip와 0.1%min로 나타났다. Ti-실리사이드 FEA는 Si FEA에 비해 낮은 turn-on 전압, 높은 전계방출전류 및 고내구특성을 나타내었다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.12
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• pp.77-82
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• 1996

The breakdown characteristics of metal-oxide-semiconductor(MOS) capacitors fabricated by Al, polysilicon, and tungsten polycide gate electrodes onto gate oxide was evaluated by time zero dielectric breakdwon (TZDB). The average breakdown field of the gate oxide with tungsten polycide electride was lower than that of the polysilicon electrode. The B model (1~8MV/cm) failure of the gate oxide with tungsten polycide electrode was increased with increasing annealing temperature in the dry $O_{2}$ ambient. This is attributed ot fluorine and tungsten diffusion from thungsten silicide film into the gate oxide, and stress increase of tungsten polcide after annealing treatment.

• The Korean Journal of Ceramics
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• v.7 no.2
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• pp.70-73
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• 2001

Phase transformation of TiSi$_2$ confined in sub-micron area of which the size is around or smaller than the grain size of C49 TiSi$_2$ phase is studied. It has been known that the C49 to C54 phase change is massive transformation that occurs abruptly starting from C54 nuclei located at triple point grain boundaries of C49 phase. When the C49 phase is confined in sub-micron area, however, the massive phase transformation is observed to be hindered due to the lack of the triple point grain boundaries of C49 phase. Heat treatment at higher temperatures starts to decompose the C49 phase, and the resulting decomposed Ti atoms diffuse to, and react with, the underneath Si material to form C54 phase that exhibits spherical interface with silicon. The newly formed C54 grains can also trigger the massive phase transformation to convert the remaining undecomposed C49 grains to C54 grains by serving as nuclei like conventional C54 nuclei located at triple point grain boundaries.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.8
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• pp.89-98
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• 1992

IIM(Implantation Into Metal) process usning Co silicides has been investigated to obtain ultra-shallow junctions less than 0.1$\mu$m. Rapid Thermal Annealing using halogen lamps was employed to form CoSi$_2$ and junctions simultaneously.. Resistivities of CoSi$_2$ were 13-17$\mu$ $\Omega$-cm. CoSi$_2$/p$^{+}$/Si and CoSi$_2$/n$^{+}$/Si junction were formed by diffusion of B and As, respectively, from Co film. It was found out that B and As were severely lost by the evaporation during high temperature annealing Therefore SiO$_2$ capping layers were introduced to prevent the evaporation of the implanted dopants from the films. Investigation of the behavior of dopants with respect to annealing time revealed that increasing the annealing time enhanced the diffusion of dopants into Si from CoSi$_2$.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.671-674
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• 2003

본 논문에서는 Cobalt interlayer 와 Titanium Nitride(TiN) capping layer를 Ni SALICIDE의 단점인 열 안정성과 sheet resistance 와 series 저항을 감소시키는데 적용하여 0.lum 급 CMOS 소자의 특성을 연구하였다. 첫째로, Ni/Si 의 interface 에 Co interlayer 를 증착하여 Nickel Silicide의 단점인 열 안정성 평가인 700℃, 30min의 furnace annealing 후에 낮은 sheet resistance와 누설전류를 줄일 수 있었다. 두번째로, TiN caping layer를 적용하여 실리사이드 형성시 산소와의 반응을 막아 실리사이드의 표면특성을 향상시켜 누설전류의 특성을 개선하였다. 결과적으로 소자의 구동전류 향상, 누설전류 저하, 낮은 면저항으로 소자의 특성을 개선하였다.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.225-228
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• 2001

We simulated and analyzed the flicker phenomena in the poly-Si TFT-LCD using PSpice for the development of wide-area and high-quality LCD display We define the electric quantity of flicker in the TFT-LCD, which is the ratio of half frame frequency (30Hz) to DC (0 Hz) frequency. We compared two different types of TFTs, excimer laser annealed (ELA) poly-Si TFT and silicide mediated crystallization (SMC) poly-Si TFT, and found that the ELA and SMC TFTs show different flicker characteristics because of their mobility and leakage current. In addition, we showed that the gate voltage should be chosen carefully at the minimum flicker because of the larger leakage current of poly-Si Tn as compared with a-Si TFT