• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.7
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• pp.42-48
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• 1994

In this paper, a low power and high speed flash Analog-to-Digital Converter using current-mode concept is proposed. Current-mode approach offers a number of advantages over conventional voltage-mode approach, such as lower power consumption small chip area improved accuracy etc. Rescently this concept was applied to algorithmic A/D Converter. But, its conversion speed is limited to medium speed. Consequently this converter is not applicable to the high speed signal processing system. This ADC is fabricated in 1.2um double metal CMOS standard process. This ADC's conversion time is measured to be 7MHz, and power consumption is 2.0mW, and differential nonlinearity is less than 1.14LSB and total harmonic distortion is -50dB. The active area of analog chip is about 350 x 550u$m^2$. The proposed ADC seems suitable for a single chip design of digital signal processing system required high conversion speed, high resolution small chip area and low power consumption.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
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• 2002.02a
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• pp.358-361
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• 2002

The millirneterwave high-T$_{c}$ superconducting(HTS) down-converter sub-system with the HTS/III-V integrated mixer as the central device is demonstrated first. The constituent components of HTS down-converter sub-system such as a single balanced type integrated mixer with rat-race coupler, a cavity type bandpass filter (26 GHz), and a HTS planar lowpass filter(1 GHz), semiconductor LNA and IF-power amplifier, a driving electronic module for A/D converter, and a Stirling type mini-cooler module were combined into an International stand- and rack of 19-inch. From the RF(-61 dBm, 26.5GHz)and LO signal(-1 dBm, 25.6 GHz), IF signal(0dBm, 0.9 GHz) agreed with simulated results is obtained.d.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.309-313
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• 1990

Pulse width modulation using discontinuous conduction modes are applied to a full-bridge series resonant converter to regulate the output from no load to full load with low switching loss and a narrow range of frequency variation. Finally, a simple nonlinear discrete-time dynamic model for this proposed converter is derived using approximation. This discrete time model is linearized and a general input - output transfer function for the propelled converter is derived.

• Publications of The Korean Astronomical Society
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• v.22 no.3
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• pp.83-87
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• 2007

We designed the Intermediate Frequency(IF) distributor for multi beam backend system and manufactured Voltage to Frequency Converter(VFC) to measure the multi-beam receiver performance. Multi beam receiver has 15 channel receivers and can get 15 spectrums at once. The multi beam receiver has more observation efficiency than single beam receiver. We manufactured the 15 IF distributors to distribute IF signal for Autocorrelation spectrometer that is radio signal processor. Also, we manufactured the VF Converter to test the performance measurement of receiver for Korea VLBI Network(KVN) system which is under-construct in Seoul, Ulsan and Jeju. As a result of performance measurement, we could obtain linearity of 99.4% on the input power vs output frequency and measured the operating range of input frequency.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1802-1812
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• 2016

Cross regulation is a key technical issue of single-inductor multiple-output (SIMO) DC-DC converters. This paper investigates the cross regulation in single-inductor dual-output (SIDO) Buck converters with continuous conduction mode (CCM) operation. The expressions of the DC voltage gain, control to the output transfer function, cross regulation transfer function, cross coupled transfer function and impedance transfer function of the converter are presented by the time averaging equivalent circuit approach. A small signal model of a SIDO CCM Buck converter is built to analyze this cross regulation. The laws of cross regulation with respect to various load conditions are investigated. Simulation and experiment results verify the theoretical analysis. This study will be helpful for converter design to reduce the cross regulation. In addition, a control strategy to reduce cross regulation is performed.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.98-107
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• 1993

This paper describes a design of a multi-bit oversampling noise-shaping D/A converter which achieves a resolution of 12 bits using oversampling technique. In the architecture the essential block which determines the whole accuracy is the analog internal D/A converter, and the designed charge-integration internal D/A converter adopts a differential structure in order to minimize the reduction of the resolution due to process variation. As the proposed circuit is driven by signal clocks which contains the information of the data variation from the noise-shaping coder, it minimizes the disadvantage of a charge-integration circuit in the time axis. In order to verify the circuit, it was integrated with the active area of 950$\times$650${\mu}m^{2}$ in a double metal 1.5-$\mu$m CMOS process, and testified that it can achieve a S/N ratio of 75 dB and a S/(N+D) ratio of 60 dB for the signal bandwidth of 9.6 kHz by the measurement with a spectrum analyzer.

• Korean Journal of Optics and Photonics
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• v.14 no.3
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• pp.215-218
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• 2003

A 2R O/E/O wavelength converter is useful for bit rate transparency, though it has a limit on cascadability due to timing-jitter accumulation. In this paper, we propose a nonlinear signal model which is more practical than the commonly used sine wave model. With our model, we theoretically analyzed the effects of timing-jitter and the cascadability of a 2R O/E/O wavelength converter. To confirm the theoretical results, we measured the cascadability in a 40-km re-circulation loop for 10 Gb/s signal.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.6
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• pp.985-993
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• 2008

This paper proposes a new DFIG(Doubly-Fed Induction Generator) system using matrix converter, which is very effectively used for interconnecting the wind power system to the power grid. The operation of proposed system was verified by computer simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was conformed by experimental works with a laboratory scaled-model of wind power system. The laboratory scaled-model was built using a motor-generator set with vector drive system, and a matrix converter with DSP(Digital Signal Processor). The operation of scaled-model was tested by modeling the specific variable-speed wind turbine using the real wind data in order to make the scaled-model simulate the real wind power system as close as possible. The simulation and experimental results confirm that matrix converter can be applied for the DFIG system.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.173-176
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• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s for video applications. Proposed architecture is designed low power A/D converter that pipelined architecture consists of flash A/D converter. This architecture consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using $0.25{\mu}m$ CMOS technology The SNR is 76.3dB at a sampling rate of 10MHz with 3.9MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}0.5/{\pm}2$ LSB, respectively. The power consumption is 13mW at 10Msample/s.