• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2005년도 추계종합학술대회
• /
• pp.887-890
• /
• 2005

DGMOSFET는 CMOS 스케일링의 확장 및 단채널 효과를 보다 효과적으로 제어할 수 있는 유망란 소자이다. 특히 20nm이하의 도핑되지 않은 Si 채널에서 단채널 효과를 제어하는데 가장 효과적이다. 본 논문에서는 DGMOSFET의 해석학적 전송모델을 제시할 것이다. 단채널 효과를 해석학적으로 분석하기 위해 Subthreshold Swing(SS), 그리고 문턱전압 roll-off(${\Delta}V_{th}$) 등을 이용하였다. 여기서 제시된 모델은 이온방출효과와 source-drain 장벽을 통해 캐리어들의 양자 터널링을 포함하여 해석할 것이다. 여기서 제시된 모델은 gate길이, 채널두께, 게이트 산화막 두께 등을 설계하는데 이용할 것이다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제14권5호
• /
• pp.572-578
• /
• 2014

In order to overcome small current drivability of a tunneling field-effect transistor (TFET), a TFET using Schottky barrier (SBTFET) is proposed. The proposed device has a metal source region unlike the conventional TFET. In addition, dopant segregation technology between the source and channel region is applied to reduce tunneling resistance. For TFET fabrication, spacer technique is adopted to enable self-aligned process because the SBTFET consists of source and drain with different types. Also the control device which has a doped source region is made to compare the electrical characteristics with those of the SBTFET. From the measured results, the SBTFET shows better on/off switching property than the control device. The observed drive current is larger than those of the previously reported TFET. Also, short-channel effects (SCEs) are investigated through the comparison of electrical characteristics between the long- and short-channel SBTFET.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제12권4호
• /
• pp.377-387
• /
• 2012

An intrinsic small signal equivalent circuit model of Cylindrical/Surrounded gate MOSFET is proposed. Admittance parameters of the device are extracted from circuit analysis and intrinsic circuit elements are presented in terms of real and imaginary parts of the admittance parameters. S parameters are then evaluated and justified with the simulated data extracted from 3D device simulation.

• 한국정보통신학회논문지
• /
• 제10권3호
• /
• pp.479-485
• /
• 2006

이중게이트 MOSFET는 스케일링 이론을 확장하고 단채널효과를 제어 할 수 있는 소자로서 각광을 받고 있다. 단 채널효과를 제어하기 위하여 저도핑 초박막 채널폭을 가진 이중게이트 MOSFET의 경우, 20nm이하까지 스케일링이 가능한 것으로 알려지고 있다. 이 논문에서 는 20m이하까지 스켈링된 이중게이트 MOSFET소자에 대한 분석학석 전송모델을 제시하고자 한다. 이 모델을 이용하여 서브문턱스윙(Subthreshold swing), 문턱전압변화(Threshold voltage rolloff) 드레인유기장벽저하(Drain induced barrier lowering)와 같은 단채널효과를 분석하고자 한다. 제안된 모델은 열방출 및 터널링에 의한 전송효과를 포함하고 있으며 이차원 포아슨방정식의 근사해를 이용하여 포텐셜 분포를 구하였다. 또한 터널링 효과는 Wentzel-Kramers-Brillouin 근사를 이 용하였다. 이 모델을 사용하여 초박막 게이트산화막 및 채널폭을 가진 5-20nm 채널길이의 이중게이트 MOSFET에 대한 서브문턱영역의 전송특성을 해석하였다. 또한 이 모델의 결과값을 이차원 수치해석학적 모델값과 비교하였으며 게이트길이, 채널두께 및 게이트산화막 두께에 대한 관계를 구하기 위하여 사용하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권1호
• /
• pp.91-105
• /
• 2016

Carbon Nanotube Field-Effect Transistors (CNTFETs) have been studied as candidates for post Si CMOS owing to the better electrostatic control and high mobility. To enhance the immunity against short - channel effects (SCEs), the novel channel and gate engineered architectures have been proposed to improve CNTFETs performance. This work presents a comprehensive study of the influence of channel and gate engineering on the CNTFET switching, high frequency and circuit level performance of carbon nanotube field-effect transistors (CNTFETs). At device level, the effects of channel and gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self - consistently with Poisson's equations. It is revealed that hetero - material - gate and lightly doped drain and source CNTFET (HMG - LDDS - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, improve the switching speed, and is more suitable for use in low power, high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the impact of the channel and gate engineering on basic digital circuits (inverter, static random access memory cell) have been investigated systematically. The performance parameters of circuits have been calculated and the optimum metal gate workfunction combinations of ${\Phi}_{M1}/{\Phi}_{M2}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product (PDP). In addition, we discuss and compare the CNTFET-based circuit designs of various logic gates, including ternary and binary logic. Simulation results indicate that LDDS - HMG - CNTFET circuits with ternary logic gate design have significantly better performance in comparison with other structures.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제11권3호
• /
• pp.182-189
• /
• 2011

In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field-effect transistor (I-HTFET) adopting $Ge-Al_xGa_{1-x}As-Ge$ system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2).