• Title/Summary/Keyword: shared parallel systems

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Incremental Design of MIN using Unit Module (단위 모듈을 이용한 MIN의 점증적 설계)

  • Choi, Chang-Hoon;Kim, Sung-Chun
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.2
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    • pp.149-159
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    • 2000
  • In this paper, we propose a new class of MIN (Multistage Interconnection Network) called SCMIN(ShortCut MIN) which can form a cheap and efficient packet switching interconnection network. SCMIN satisfies full access capability(FAC) and has multiple redundant paths between processor-memory pairs even though SCMIN is constructed with 2.5N-4 SEs which is far fewer SEs than that of MINs. SCMIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. Therefore, SCMIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

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Development of a Hydraulic Level Control System for High-speed Rice Transplanting Machines (고속 이앙기의 유압 수평 제어 장치 개발에 관한 연구)

  • 정연근;정병학;김경욱
    • Journal of Biosystems Engineering
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    • v.27 no.2
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    • pp.79-88
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    • 2002
  • This study was conducted to develop system for high speed rice transplanting machines. The control system includes a sensor detecting the tilt angle of the seedling bed, a micro-controller and a hydraulic system consisting of a double acting cylinder, a four-way three-position solenoid valve, a relief valve and a hydraulic pump. The levelling system shared the pump with the existing steering control, resulting in a tandem center circuit for the steering and levelling control systems. Using the input signal from the sensor, the micro-controller determined and generated the output signal to control the cylinder through the solenoid valve to keep the seedling bed always parallel to the water surface regardless of soil unevenness during the transplanting operations. Both an ON/OFF and a PWM control schemes were tested. When the flow rate was more than 1 ι/min in the ON/OFF control, the system showed unstable rolling. However, in the PWM control, the system worked stably although the flow rate was more than 1 ι/min. The PWM control showed a better performance when a large difference between the angle and the dead band of the control system occurred. The characteristics of tile system response to given tilt angles were predicted by a computer simulation. Both the ON/OFF and the PWM control systems worked well providing that the operating and waiting times were properly adjusted.

A Study on Efficient Executions of MPI Parallel Programs in Memory-Centric Computer Architecture

  • Lee, Je-Man;Lee, Seung-Chul;Shin, Dongha
    • Journal of the Korea Society of Computer and Information
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    • v.25 no.1
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    • pp.1-11
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    • 2020
  • In this paper, we present a technique that executes MPI parallel programs, that are developed on processor-centric computer architecture, more efficiently on memory-centric computer architecture without program modification. The technique we present here improves performance by replacing low-speed data communication over the network of MPI library functions with high-speed data communication using the property called fast large shared memory of memory-centric computer architecture. The technique we present in the paper is implemented in two programs. The first program is a modified MPI library called MC-MPI-LIB that runs MPI parallel programs more efficiently on memory-centric computer architecture preserving the semantics of MPI library functions. The second program is a simulation program called MC-MPI-SIM that simulates the performance of memory-centric computer architecture on processor-centric computer architecture. We developed and tested the programs on distributed systems environment deployed on Docker based virtualization. We analyzed the performance of several MPI parallel programs and showed that we achieved better performance on memory-centric computer architecture. Especially we could see very high performance on the MPI parallel programs with high communication overhead.

Scalable and Dynamically Reconfigurable Internet Service System Based on Clustered System (확장과 동적재구성 가능한 클러스터기반의 인터넷서비스 시스템)

  • Kim Dong Keun;Park Se Myung
    • Journal of Korea Multimedia Society
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    • v.7 no.10
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    • pp.1400-1411
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    • 2004
  • Recently, explosion of internet user requires fundamental changes on the architecture of Web service system, from single server system to clustered server system, in parallel with the effort for improving the scalability of the single internet server system. But current cluster-based server systems are dedicated to the single application, for example, One-IP server system. One-IP server system has a clustered computing node with the same function and tries to distribute each request based on the If to the clustered node evenly. In this paper, we implemented the more useful application service platform. It works on shared clustered server(back-end server) with an application server(front-end server) for a particular service. An application server provides a particular service at a low load by itself, but as the load increases, it reconfigures itself with one or more available server from the shared cluster and distributes the load on selected server evenly We used PVM for an effective management of the clustered server. We found the implemented application service platform provides more stable and scalable operation characteristics and has remarkable performance improvement on the dynamic load changes.

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Reconfigurable Architecture Design for H.264 Motion Estimation and 3D Graphics Rendering of Mobile Applications (이동통신 단말기를 위한 재구성 가능한 구조의 H.264 인코더의 움직임 추정기와 3차원 그래픽 렌더링 가속기 설계)

  • Park, Jung-Ae;Yoon, Mi-Sun;Shin, Hyun-Chul
    • Journal of KIISE:Computer Systems and Theory
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    • v.34 no.1
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    • pp.10-18
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    • 2007
  • Mobile communication devices such as PDAs, cellular phones, etc., need to perform several kinds of computation-intensive functions including H.264 encoding/decoding and 3D graphics processing. In this paper, new reconfigurable architecture is described, which can perform either motion estimation for H.264 or rendering for 3D graphics. The proposed motion estimation techniques use new efficient SAD computation ordering, DAU, and FDVS algorithms. The new approach can reduce the computation by 70% on the average than that of JM 8.2, without affecting the quality. In 3D rendering, midline traversal algorithm is used for parallel processing to increase throughput. Memories are partitioned into 8 blocks so that 2.4Mbits (47%) of memory is shared and selective power shutdown is possible during motion estimation and 3D graphics rendering. Processing elements are also shared to further reduce the chip area by 7%.

An Online Scaling Method for Improving the Availability of a Database Cluster (데이터베이스 클러스터의 가용성 향상을 위한 온라인 확장 기법)

  • Lee, Chung-Ho;Jang, Yong-Il;Bae, Hae-Yeong
    • The KIPS Transactions:PartD
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    • v.10D no.6
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    • pp.935-948
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    • 2003
  • An online scaling method adds new nodes to the shared-nothing database cluster and makes tables be reorganized while the system is running. The objective is to share the workload with many nodes and increase the capacity of cluster systems. The existing online scaling method, however, has two problems. One is the degradation of response time and transactions throughput due to the additional overheads of data transfer and replica's condidtency. The other is and inefficient recovery mechanism in which the overall scaling transaction is aborted by a fault. These problems deteriorate the availability of shared-nothing database cluster. To avoid the additional overheads throughout the scaling period, our scalingmethod consists of twophases : a parallel data transfer phase and a combination phase. The parallel data transferred datausing reduces the size of data transfer by dividing the data into the number of replicas. The combination phase combines the transferred datausing resources of spare nodes. Also, our method reduces the possibility of failure throughout the scaling period and improves the availability of the database cluster.

Page replication mechanism using adjustable DELAY counter in NUMA multiprocessors (NUMA 다중처리기에서 조정가능한 지연 카운터를 이용한 페이집 복사 기법)

  • 이종우;조유곤
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.6
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    • pp.23-33
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    • 1996
  • The exploitation of locality of reference in shared memory NUMA multiprocessors is one of the improtant problems in parallel processing today. In this paper, we propose a revised hardeare reference counter to help operating system to manage locality. In contrast to the previous one, the value of counter can abe adjusted dynamically and periodically to adapt the page replication policy to the various memory reference patterns of processors. We use execution-driven simulation of real applications to evaluate the effectiveness of our adjustable DELAY counter. Our main conclusijon is that by using the adjustable DELAY counter the t normalized average memory access costs and the variance of them become smaller for most applications than the previous one and more robust memory management policies can be provided for the operating systems.

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Design and Simulation of Interconnection Network Based on Topological Combination (위상 결합을 기반으로 한 연결 망 설계 및 시뮬레이션)

  • 장창수;최창훈
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.6B
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    • pp.563-574
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    • 2004
  • In this paper, we propose a new class of MIN(Multistage Interconnection Network) called Combine MIN which combines static network topology and apimic network topology. Combine U provides multiple paths at a hardware cost lower than that of MIN with unique path property. Combine MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. According to the results of analysis and simulation for performance evaluation, Combine MIN shows higher performance than MINs of the same network size in the highly localized communication Therefore, Combine MIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

Performance Analysis of a Multiprocessor System Using Simulator Based on Parsec (Parsec 기반 시뮬레이터를 이용한 다중처리시스템의 성능 분석)

  • Lee Won-Joo;Kim Sun-Wook;Kim Hyeong-Rae
    • Journal of the Korea Society of Computer and Information
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    • v.11 no.2 s.40
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    • pp.35-42
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    • 2006
  • In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

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Main Memory Spatial Database Clusters for Large Scale Web Geographic Information Systems (대규모 웹 지리정보시스템을 위한 메모리 상주 공간 데이터베이스 클러스터)

  • Lee, Jae-Dong
    • Journal of Korea Spatial Information System Society
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    • v.6 no.1 s.11
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    • pp.3-17
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    • 2004
  • With the rapid growth of the Internet geographic information services through the WWW such as a location-based service and so on. Web GISs (Geographic Information Systems) have also come to be a cluster-based architecture like most other information systems. That is, in order to guarntee high quality of geographic information service without regard to the rapid growth of the number of users, web GISs need cluster-based architecture that will be cost-effective and have high availability and scalability. This paper proposes the design of the cluster-based web GIS with high availability and scalability. For this, each node within a cluster-based web GIS consists of main memory spatial databases which accomplish role of caching by using data declustering and the locality of spatial query. Not only simple region queries but also the proposed system processed spatial join queries effectively. Compare to the existing method. Parallel R-tree spatial join for a shared-Nothing architecture, the result of simulation experiments represents that the proposed spatial join method achieves improvement of performance respectively 23% and 30% as data quantity and nodes of cluster become large.

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