• 한국표면공학회지
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• 제31권5호
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• pp.237-244
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• 1998

In this stydy, submicron shallow trenches applied to STI(shallow tench isolation) were etched using inductively coupled $CI_2$/HBr and $CI_2/N_2$plasmas and the physical and electrical defects remaining on the etched silicon trench surfaces and the effects of various annealing and oxidation on the removal of the defects were studied. Using high resolution electron microscopy(HRTEM), Physical defects were investigated on the silicon trench surfaces etched in both 90%$CI_2$/ 10%$N_2$ and 50%$CI_2$/50%HBr. Among the areas in the tench such as trench bottom, bottom edge, and sidewall, the most dense defects were found near the trench bottom edge, and the least dense defects were found near the trench bottom edge, and least dense defects compared to that etched with ment as well as hydrogen permeation. Thermal oxidation of 200$\AA$ atthe temperature up to $1100^{\circ}C$apprars not to remove the defects formed on the etched silicon trenches for both of the etch conditions. To remove the physicall defects, an annealing treatment at the temperature high than $1000^{\circ}C$ in N for30minutes was required. Electrical defects measured using a capacitance-voltage technique showed the reduction of the defects with increasing annealing temperature, and the trends were similar to the results on the physical defects obtained using transmission electron microscopy.

• 한국세라믹학회:학술대회논문집
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• 한국세라믹학회 2003년도 춘계총회 및 연구발표회 초록집
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• pp.78.2-78
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• 2003

• 한국재료학회:학술대회논문집
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• 한국재료학회 2004년도 춘계학술발표대회 및 제6회 신소재 심포지엄
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• pp.64-64
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• 2004

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.78.2-78
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• 1998

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.106.1-106
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• 1998

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.41-44
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• 2000

Ultra large scale integrated circuit(ULSI) & complementary metal oxide semiconductor(CMOS) circuits require gate electrode materials such as meta] silicides, titanium-silicide for gate oxides. Many previous authors have researched the improvements sub-micron gate oxide quality. However, little has been done on the electrical quality and reliability of ultra thin gates. In this research, we recommend novel shallow trench isolation structure and two step TiSi$_{2}$ formation for sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2003년도 학술대회지
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• pp.402-402
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• 2003

• Transactions on Electrical and Electronic Materials
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• 제8권1호
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (2)
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• pp.674-676
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• 1998

소자가 sub-quarter um급으로 축소됨에 따라 STI(Shallow Trench Isolation) 기술은 고 집적도의 ULSI 구현에 있어서 중요한 격리 방법으로 많이 사용되고 있다. 현재의 STI 기술은 주로 실리콘 기판을 식각 후 절연물질로 빈 공백이 없이 채우는 (void-free gap filling) 방법 [1,2]과 절연물질을 다시 표면 근처까지 CMP(Chemical Mechnical Polishing)로 etchback하여 평탄화를 하는 방법이 주요한 기술이 되고 있다. 또한 STI 구조로된 격리구조에서 만들어진 MOSFET의 전기적인 특성은 트랜치 격리의 상부 부분의 형태와 gap-filling 물질에 따라 큰 영향을 받게된다. 따라서 본 논문에서는 STI 구조로 만들어진 격리 구조에서 MOSFET의 hump 특성에 관해 연구하였다. 그 결과 hump는 STI 모서리에서 필드 옥사이드의 recess에 의한 모서리 부분에서의 전계 집중과 boron의 segration에 기인한 농도 감소로 인해 hump가 발생하는 것으로 나타났다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.14-17
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• 2000

The rise throughput and the stability in fabrication of device can be obtained by applying of CMP process to STI structure in 0.18um semiconductor device. To employ in STI CMP, the reverse moat process has been added thus the process became complex and the defects were seriously increased. Removal rates of each thin films in STi CMP was not equal hence the devices must to be effected, that is, the damage was occured in the device dimension in the case of excessive CMP process and the nitride film was remained on the device dimension in the case of insufficient CMP process than these defects affect the device characteristics. We studied the current sensing method in STI-CMP with the reverse moat pattern.