• Journal of information and communication convergence engineering
• /
• v.10 no.2
• /
• pp.194-199
• /
• 2012

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, which uses a down literal circuit (DLC) with a floating-gate metal-oxide semiconductor transistor (FGMOS) based on a neuron model. The detection circuit is designed and simulated in a 3.3 V, 0.35 ${\mu}m$ standard CMOS process. Because the proposed circuit does not need a comparator and peripheral circuits, the pixel layout size can be reduced and the image resolution can be improved.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.11 no.2
• /
• pp.330-336
• /
• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.16 no.6
• /
• pp.465-471
• /
• 2023

This paper proposes a comparator structure that improves the noise and output delay of a single-slope ADC(SS-ADC) used in CMOS Image Sensor (CIS). To improve the noise and delay characteristics of the output, a comparator structure using the miller effect is designed by inserting a capacitor between the output node of the first stage and the output node of the second stage of the comparator. The proposed comparator structure improves the noise, delay of the output, and layout area by using a small capacitor. The CDS counter used in the single slop ADC is designed using a T-filp flop and bitwise inversion circuit, which improves power consumption and speed. The single-slope ADC also performs dual CDS, which combines analog correlated double sampling (CDS) and digital CDS. By performing dual CDS, image quality is improved by reducing fixed pattern noise (FPN), reset noise, and ADC error. The single-slope ADC with the proposed comparator structure is designed in a 0.18-㎛ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.571-574
• /
• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.3
• /
• pp.531-536
• /
• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.15 no.1
• /
• pp.61-70
• /
• 2020

In this study, the IOT-based desk layout method was proposed to complement the existing seating method and to improve the work efficiency. The IoT system for the desk layout needs determining the function, type and network protocol of the sensor to find out the working status of the desk to reasonably assist the worker's seat placement. A collection method was proposed. The algorithm used in Block Stacking was used when deciding how to allocate seats using the acquired data. As a result, we could suggest an arithmetic basis for rational desk layout in IoT environment and show that it can be applied to an advanced flexible seating system based on working type in addition to the preferences of employees in the future.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.45 no.7
• /
• pp.9-16
• /
• 2008

For the efficient routing on a Sensor Network, one may consider a deployment problem to interconnect the sensor nodes optimally. There is an analogous theoretic problem: the Steiner Tree problem of finding the tree that interconnects given points on a plane optimally. One may use the approximation algorithm for the problem to find out the deployment that interconnects the sensor nodes almost optimally. However, the Steiner Tree problem is to interconnect mathematical set of points on a Euclidean plane, and so involves particular cases that do not occur on Sensor Networks. Thus the approach of using the algorithm does not make a proper way of analysis. Differently from the randomly given locations of mathematical points on a Euclidean plane, the locations of sensors on Sensor Networks are assumed to be physically dispersed over some moderate distance with each other. By designing an approximation algorithm for the Sensor Networks in terms of that physical property, one may produce the execution time and the approximation ratio to the optimality that are appropriate for the problem of interconnecting Sensor Networks.

• Journal of Sensor Science and Technology
• /
• v.4 no.4
• /
• pp.55-61
• /
• 1995

A new ISFET array chip, based on detection of the threshold voltages of ISFETs by using an adjustable input, was designed. The chip includes 240 pH-ISFETs and circuitry such as comparators, a decoder and register. The chip has increased reliability, improved accuracy, digital output capability and the possibility of multi sensor implementation. To fabricate the chip, an extended CMOS process was devised and implemented.

• Smart Structures and Systems
• /
• v.20 no.6
• /
• pp.759-767
• /
• 2017

Wear and aging associated damage is a severe problem for safety and maintenance of engineering structures. To acquire structural operational state and provide warning about different types of damage, research on damage identification has gained increasing popularity in recent years. Among various damage identification methods, the Lamb wave-based methods have shown promising suitability and potential for damage identification of plate-type structures. In this paper, a comprehensive study was presented to elaborate four remarkable aspects regarding the Lamb wave-based damage identification method for plate-type structures, including wave velocity, signal denoising, image reconstruction, and sensor layout. Conclusions and path forward were summarized and classified serving as a starting point for research and application in this area.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.6
• /
• pp.1343-1348
• /
• 2011

A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than a conventional circuit. The detection circuit is designed and simulated in 3.3V, $0.35{\mu}m$ standard CMOS process, 40MHz condition. The result shows about 47% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is layout without area increasing of a one pixel.