• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.04a
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• pp.921-926
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• 1997

SOI(Silicon On lnsulator) technology is many advantages in the gabrication of MOS(Metal-Oxide Semiconductor) and CMOS(Complementary MOS) structures. These include high speed, lower dynamic power consumption,greater packing density, increased radiation tolearence et al. In smiple form of bonded SOL wafer manufacturing, creation of a bonded SOI structure involves oxidizing at least one of the mirror polished silicon surfaces, cleaning the oxidized surface and the surface of the layer to which it will be bonded,bringing the two cleanded surfaces together in close physical proximity, allowing the subsequent room temperature bonding to proceed to completion, and than following this room temperature joining with some form of heat treatment step,and device wafer is thinned to the target thickness. This paper has been performed to investigate the possibility of the bonded SOI wafer manufacturing Especially, we focused on the bonding quality and thinning method. Finally,we achieved the bonded SOI wafer that Si layer thickness is below 3 .mu. m and average roughness is below 5.angs.

• Journal of Magnetics
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• v.10 no.2
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• pp.41-43
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• 2005

We have investigated an optical waveguide isolator with a multimode interference section by wafer direct bonding, operating at a wavelength $1.55\;{\mu}m$. In order to fabricate the device for monolithic integration, the wafer direct bonding between a magnetic garnet material as a cladding layer and a semiconductor guiding layer has been achieved. We found that wafer direct bonding between InP and GGG $(Gd_3Ga_5O_{12})$ is effective for the integration of a waveguide optical isolator. The isolation ratio was obtained to be 2.9 dB in the device.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.72.2-72
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• 1998

• 제어로봇시스템학회:학술대회논문집
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• 1988.10a
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• pp.353-359
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• 1988

In this paper, the design and implementation of a multi-processor based die bonder machine for the semiconductor will be described. This is a final research results carried out for two years from June, 1986 to July, 1988. The mechanical system consists of three subsystems such as bonding head module, wafer feeding module, and lead frame feeding module. The overall control system consists of the following three subsystems each of which employs a 16 bit microprocessor MC 68000 : (i) supervisory control system, (ii) visual recognition / inspection system and (iii) the display system. Specifically, the supervisory control system supervises the whole sequence of die bonder machine, performs a self-diagnostics while it controls the bonding head module according to the prespecified bonding cycle. The vision system recognizes the die to inspect the die quality and deviation / orientation of a die with respect to a reference position, while it controls the wafer feeding module. Finally, the display system performs a character display, image display ans various error messages to communicate with operator. Lead frame feeding module is controlled by this subsystem. It is reported that the proposed control system were applied to an engineering sample and tested in real-time, and the results are sucessful as an engineering sample phase.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.8-13
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• 2023

High bandwidth memory a core technology of the future memory semiconductor industry, is attracting attention. Temporary bonding and debonding process technology, which plays an important role in high bandwidth memory process technology, is also being studied. In this process, total thickness variation is a major factor determining wafer performance. In this study, the reliability of the equipment measuring total thickness variation is identified, and the servo motor settling, and wafer total thickness variation measurement accuracy are analyzed. As for the experimental variables, vacuum, acceleration time, and speed are changed to find the most efficient value by comparing the stabilization time. The smaller the vacuum and the larger the radius, the longer the settling time. If the radius is small, high-speed rotation performance is good, and if the radius is large, low-speed rotation performance is good. In the future, we plan to conduct an experiment to measure the entire of the wafer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.6 no.4
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• pp.34-38
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• 1997

This paper presents a joining method by using the silicon wafer in order to apply to joint to the 3-dimensional structures of semiconductor device, high-speed , high integration, micro machine, silicon integrated sensor, and actuator. In this study, the high atomic beam, stabilized by oxidation film and organic materials at the material surface, is investigated, and the purified is obtained by removing the oxidation film and pollution layer at the materials. And the unstable surface is obtained, which can be easily joined. In order to use the low temperatures for the joint method, the main subjects are obtained as follows: 1) In the case of the silicon wafer and the silicon wafer and the silicon wafer of alumina sputter film, the specimens can be jointed at 2$0^{\circ}C$, and the joining strength is 5Mpa. 2) The specimens can not always be joined at the room temperatures in the case of the silicon wafer and the silicon wafer of alumina sputter film.

• Journal of the Korean Society for Precision Engineering
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• v.22 no.6 s.171
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• pp.144-151
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• 2005

Spin coater is regarded as a major module rotating at high speed to be used build up polymer resin thin film layer fur bonding process of GaAs wafer. This module is consisted of spin unit for spreading uniformly, align device, resin spreading nozzle and et. al. Specially, spin unit which is a component of module can cause to vibrate and finally affect to the uniformity of polymer resin film layer. For the stability prediction of rotation velocity and uniformity of polymer resin film layer, it is very important to understand the dynamic characteristics of assembled spin coater module and the dynamic response mode resulted from rotation behavior of spin chuck. In this paper, stress concentration mode and the deformed shape of spin chuck generated due to angular acceleration process are presented using analytical method for evaluation of structural safety according to the revolution speed variation of spin unit. And also, deformation form of GaAs wafer due to dynamic behavior of spin chuck is presented fur the comparison of former simulated results.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.5 s.98
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• pp.40-47
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• 1999

In CMP for semiconductor wafer films, the acceptable within-chip planarity, within-wafer and wafer-to-wafer nonuniformity could be achieved by conditioning. The role of conditioning is to remove continuously polishing residues from pad and to maintain the initial pad surface pores. To reach these requirements, the diamond grits disk has been considered as a conventional conditioner. However, we have investigated many defects as scratch on wafers out of diamond grits shedding, contaminations from bonding materials, and pad pore subsidences by over-conditioning. So, this paper studies the effect of ultrasonic vibration in CMP conditioning as a representative. The effect of ultrasonic vibration was certified through ILD, Metal CMP.

• Journal of the Semiconductor & Display Technology
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• v.1 no.1
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• pp.15-19
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• 2002

A new vacuum packaging process in wafer level is developed for the surface micromachining devices using glass silicon anodic bonding technology. The inside pressure of the packaged device was measured indirectly by the quality factor of the mechanical resonator. The measured Q factor was about 5$\times10^4$ and the estimated inner pressure was about 1 mTorr. And it is also possible to change the inside pressure of the packaged devices from 2 Torr to 1 mTorr by varying the amount of the Ti gettering material. The long-term stability test is still on the way, but in initial characterization, the yield is about 80% and the vacuum degradation with time was not observed.