• 대한기계학회논문집B
• /
• 제32권2호
• /
• pp.149-157
• /
• 2008

During CVD process of semiconductor wafer fabrication, maintaining the uniformity of temperature distribution at wafer top surface is one of the key factors affecting the quality of final products. Effect of contact conductance between wafer and hot plate on predicted temperature of wafer was investigated. The validity of opaque wafer assumption was also examined by comparing the predicted results with Discrete Ordinate solutions accounting for semitransparent radiative characteristics of silicon. As the contact conductance increases predicted wafer temperature increases and the differences between maximum and minimum temperatures within wafer and between wafer and hot plate top surface temperatures decrease. The opaque assumption always overpredicted the wafer temperature compared to semitransparent calculation. The influences of surrounding reactor inner wall temperature and hot plate configuration are then discussed.

• 반도체디스플레이기술학회지
• /
• 제9권3호
• /
• pp.47-51
• /
• 2010

This paper presents a wafer pre-alignment system which is improved using the image of the entire wafer area. In the previous method, image acquisition for wafer takes about 80% of total pre-alignment time. The proposed system uses only one image of entire wafer area via a high-resolution CMOS camera, and so image acquisition accounts for nearly 1% of total process time. The larger FOV(field of view) to use the image of the entire wafer area worsen camera lens distortion. A camera calibration using high order polynomials is used for accurate lens distortion correction. And template matching is used to find a correct notch's position. The performance of the proposed system was demonstrated by experiments of wafer center alignment and notch alignment.

• 한국신재생에너지학회:학술대회논문집
• /
• 한국신재생에너지학회 2007년도 추계학술대회 논문집
• /
• pp.232-232
• /
• 2007

• Industrial Engineering and Management Systems
• /
• 제4권1호
• /
• pp.47-53
• /
• 2005

The efficiency of fabrication (fab) operation is one of the key factors in order for a semiconductor manufacturing company to stay competitive. Optimization of manpower and forecasting manpower needs in a modern fab is an essential part of the future strategic planing and a very important to the operational efficiency. As the semiconductor manufacturing technology has entered the 8-inch wafer era, the complexity of fab operation increases with the increase of wafer size. The wafer handling method has evolved from manual mode in 6-inch wafer fab to semi-automated or fully automated factory in 8-inch and 12-inch wafer fab. The distribution of manpower requirement in each specialty varied as the trend of fab operation goes for downsizing manpower with automation and outsourcing maintenance work. This paper is to study the specialty distribution of manpower from the requirement in a typical 6-inch, 8-inch to 12-inch wafer fab. The human resource planning in today’s fab operation shall consider many factors, which include the stability of technical talents. This empirical study mainly focuses on the human resource planning, the manpower distribution of specialty structure and the forecast model of internal demand/supply in current semiconductor manufacturing company. Considering the market fluctuation with the demand of varied products and the advance in process technology, the study is to design a headcount forecast model based on current manpower planning for direct labour (DL) and indirect labour (IDL) in Taiwan’s fab. The model can be used to forecast the future manpower requirement on each specialty for the strategic planning of human resource to serve the development of the industry.

• 반도체디스플레이기술학회지
• /
• 제21권2호
• /
• pp.51-56
• /
• 2022

Recently, the demand for semiconductors is expanded to various industries, and the use of high-quality and high-performance chips is increasing. With the trend, the diameter magnification and high integration of the semiconductor wafers are mandatory. As a result, there is a growing demand for the productivity improvement and the surface precision. There have been many studies on the stabilization of the wafer manufacturing processes in order to satisfy those specifications. Many complaints have been appealed by the wafer buyers that there are many unacceptable wafers with surface defects and foreign material adhesion which are caused by the vibrations during transportation. This study intends to derive the material improvement of the packing box of the wafers to suppress the vibrations of the box, and eventually to reduce the surface defects and the foreign material adhesion. The result shows that optimal material can substantially decrease the vibration of the packing box.

• 반도체디스플레이기술학회지
• /
• 제9권1호
• /
• pp.11-16
• /
• 2010

Wafer Pre-Alignment is to find the center and the orientation of a wafer and to move the wafer to the desired position and orientation. In this paper, an area camera based pre-aligning method is presented that captures 8 wafer images regularly during 360 degrees rotation. From the images, wafer edge positions are extracted and used to estimate the wafer's center and orientation using least squares circle fitting. These data are utilized for the proper alignment of the wafer. For accurate alignments, camera calibration methods using high order polynomials are used for converting pixel coordinates into real-world coordinates. A complete pre-alignment system was constructed using mechanical and optical components and tested. Experimental results show that alignment of wafer center and orientation can be done with the standard deviation of 0.002 mm and 0.028 degree, respectively.

• 반도체디스플레이기술학회지
• /
• 제9권2호
• /
• pp.21-25
• /
• 2010

In response to the industrial needs for automated handling of very thin solar cell wafers, this paper presents the design concept for the individual wafer separation from the stacked wafers by utilizing continuous water jet. The experimental apparatus for automated wafer separation was constructed and it includes the water jet system and the microprocessor controlled wafer stack advancing system. Through a series of tests, the performance of the proposed design is quantified into the success rate of single wafer separation and the rapidity of processing wafer stack. Also, the inclination angle of wafer equipped cartridge and the water jet flowrate are found to be important parameters to be considered for process optimization. The proposed design shows the concept for fast and efficient processing of wafer separation and can be implemented in the automated manufacturing of silicon based solar cell wafers.

• 반도체디스플레이기술학회지
• /
• 제2권3호
• /
• pp.1-6
• /
• 2003

In the rapid changes of the semiconductor manufacturing technologies for early 21st century, it may be safely said that a kernel of terms is the size increase of Si wafer and the size decrease of semiconductor devices. As the size of Si wafers increases and semiconductor device is miniaturized, the units of cleaning processes increase. A present cleaning technology is based upon RCA cleaning which consumes vast chemicals and ultra pure water (UPW) and is the high temperature process. Therefore, this technology gives rise to environmental issue. To resolve this matter, candidates of advanced cleaning processes have been studied. One of them is to apply the electrolyzed water. In this work, electrolyzed water cleaning was compared with various chemical cleaning, using Si wafer surfaces by changing cleaning temperature and cleaning time, and especially, concentrating upon the contact angle. It was observed that contact angle on surface treated with Electrolyzed water cleaning was $4.4^{\circ}$ without RCA cleaning. Amine series additive of high pKa (negative logarithm of the acidity constant) was used to observe the property changes of cathode water.

• 설비공학논문집
• /
• 제5권2호
• /
• pp.130-140
• /
• 1993

Average particle deposition velocity toward a horizontal semiconductor wafer in vertical airflow is measured by a wafer surface scanner(PMS SAS-3600). Use of wafer surface scanner requires very short exposure time normally ranging from 10 to 30 minutes, and hence makes repetition of experiment much easier. Polystyrene latex (PSL) spheres of diameter between 0.2 and $1.0{\mu}m$ are used. The present range of particle sizes is very important in controlling particle deposition on a wafer surface in industrial applications. For the present experiment, convection, diffusion, and sedimentation comprise important agents for deposition mechanisms. To investigate confidence interval of experimental data, mean and standard deviation of average deposition velocities are obtained from more than ten data set for each PSL sphere size. It is found that the distribution of mean of average deposition velocities from the measurement agrees well with the predictions of Liu and Ahn(1987) and Emi et al.(1989).

• 한국CDE학회논문집
• /
• 제19권3호
• /
• pp.214-223
• /
• 2014

This paper presents a bottleneck detection framework using simulation approach in a wafer FAB (Fabrication). In a semiconductor manufacturing industry, wafer FAB facility contains various equipment and dozens kinds of wafer products. The wafer FAB has many characteristics, such as re-entrant processing flow, batch tools. The performance of a complex manufacturing system (i.e. semiconductor wafer FAB) is mainly decided by a bottleneck. This paper defines the problem of a bottleneck process and propose a simulation based framework for bottleneck detection. The bottleneck is not the viewpoint of a machine, but the viewpoint of a step with the highest WIP in its upstream buffer and severe fluctuation. In this paper, focus on the classification of bottleneck steps and then verify the steps are not in a starvation state in last, regardless of dispatching rules. By the proposed framework of this paper, the performance of a wafer FAB is improved in on-time delivery and the mean of minimum of cycle time.