• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.6
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• pp.685-694
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• 2015

In this paper, a new dynamic reference scheme is proposed to improve the read voltage margin better than the previous static reference scheme. The proposed dynamic reference scheme can be helpful in compensating not only the background pattern dependence but also the cell position dependence. The proposed dynamic reference is verified by simulating the CMOS-memristor hybrid circuit using the practical CMOS SPICE and memristor Verilog-A models. In the simulation, the percentage read voltage margin is compared between the previous static reference scheme and the new dynamic reference scheme. Assuming that the critical percentage of read voltage margin is 5%, the memristor array size with the dynamic scheme can be larger by 60%, compared to the array size with the static one. In addition, for the array size of $64{\times}64$, the interconnect resistance in the array with the dynamic scheme can be increased by 30% than the static reference one. For the array size of $128{\times}128$, the interconnect resistance with the proposed scheme can be improved by 38% than the previous static one, allowing more margin on the variation of interconnect resistance.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.7
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• pp.665-670
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• 2016

In this paper, we suggest the design of OP-AMP using MOSFET in the operation of sub-threshold condition as a basic unit of an IoT. The sub-threshold operation of MOSFET is useful for an ultra low power consumption of sensor network system in the IoT, because it cause the supply voltage to be reduced. From the simulation result using 0.35 um CMOS process, the supply voltage, VDD can be reduced with 0.6 V, open-loop gain of 43 dB and the power consumption was evaluated with about $1.3{\mu}W$ and the active size for an integration was measured with $64{\mu}m{\times}105{\mu}m$. It is expected that the proposed circuit is applied to the low power sensor network for IoT.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.4
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• pp.659-665
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• 2017

Power semiconductor devices required the low on-resistance and high breakdown voltage. Wide band-gap materials opened a new technology of the power devices which promised a thin drift layer at an identical breakdown voltage. The diamond had the wide band-gap of 5.5 eV which induced the low power loss, high breakdown capability, low intrinsic carrier generation, and high operation temperature. We investigated the p-type pseudo-vertical diamond Schottky barrier diodes using a numerical simulation. The impact ionization rate was material to calculating the breakdown voltage. We revised the impact ionization rate of the diamond for adjusting the parallel-plane breakdown field at 10 MV/cm. Effects of the field plate on the breakdown voltage was also analyzed. A conventional diamond Schottky barrier diode without field plate exhibited the high forward current of 0.52 A/mm and low on-resistance of $1.71{\Omega}-mm$ at the forward voltage of 2 V. The simulated breakdown field of the conventional device was 13.3 MV/cm. The breakdown voltage of the conventional device and proposed devices with the $SiO_2$ passivation layer, anode field plate (AFP), and cathode field plate (CFP) was 680, 810, 810, and 1020 V, respectively. The AFP cannot alleviate the concentration of the electric field at the cathode edge. The CFP increased the breakdown voltage with evidences of the electric field and potential. However, we should consider the dielectric breakdown because the ideal breakdown field of the diamond is higher than that of the $SiO_2$, which is widely used as the passivation layer. The real breakdown voltage of the device with CFP decreased from 1020 to 565 V due to the dielectric breakdown.

• Korean Journal of Materials Research
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• v.27 no.2
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• pp.107-112
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• 2017

The BCBJ (Back Contact and Back Junction) or back-lit solar cell design eliminates shading loss by placing the pn junction and metal electrode contacts all on one side that faces away from the sun. However, as the electron-hole generation sites now are located very far from the pn junction, loss by minority-carrier recombination can be a significant issue. Utilizing Medici, a 2-dimensional semiconductor device simulation tool, the interdependency between the substrate thickness and the minority-carrier recombination lifetime was studied in terms of how these factors affect the solar cell power output. Qualitatively speaking, the results indicate that a very high quality substrate with a long recombination lifetime is needed to maintain the maximum power generation. The quantitative value of the recombination lifetime of minority-carriers, i.e., electrons in p-type substrates, required in the BCBJ cell is about one order of magnitude longer than that in the front-lit cell, i.e., $5{\times}10^{-4}sec$ vs. $5{\times}10^{-5}sec$. Regardless of substrate thickness up to $150{\mu}m$, the power output in the BCBJ cell stays at nearly the maximum value of about $1.8{\times}10^{-2}W{\cdot}cm^{-2}$, or $18mW{\cdot}cm^{-2}$, as long as the recombination lifetime is $5{\times}10^{-4}s$ or longer. The output power, however, declines steeply to as low as $10mW{\cdot}cm^{-2}$ when the recombination lifetime becomes significantly shorter than $5{\times}10^{-4}sec$. Substrate thinning is found to be not as effective as in the front-lit case in stemming the decline in the output power. In view of these results, for BCBJ applications, the substrate needs to be only mono-crystalline Si of very high quality. This bars the use of poly-crystalline Si, which is gaining wider acceptance in standard front-lit solar cells.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.1031-1033
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• 2013

Radiation protection, as well as finding the location of the radiation source, such as the Fukushima radiation leak accident, it is important for the early and safe disposal of nuclear accident. The three-dimensional position of the radiation source detection distance of the radiation source can provide additional information to the existing radiation detectors radiation of a two-dimensional position detection function and then it can play a decisive role in the radiation contaminant removal and decontamination work. In this research, three-dimensional semiconductor sensor based on dual radiation detectors radiation source device visible part of the research and development of efficient radiation sensor unit on the design of the shielding structure.The lightweight, high-efficiency radiation source locator implementation was attempted for the structure and thickness of the shielding and collimator to perform the simulation of the radiation shielding for the various parameters of the shape model through design the optimal structure of the MCNP-based heavy-duty tungsten shielding, lead shielding The results of this study, is a compact, lightweight three-dimensional radiation source detection and future of silicon - based sensors will be used in the study.

• Tribology and Lubricants
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• v.33 no.2
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• pp.52-58
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• 2017

An ultra-high precise ejection process is essential in a dispensing system for fabricating various precision parts such as a semiconductor, LED, and camera module. The size of such parts has been decreasing, which implies that a precise ejecting technique is required. A phosphor-containing liquid is ejected via a dispenser using dual piezoelectric actuators that are used for generating a high-speed dispensing mechanism. The rod and nozzle continuously contact in high speed to eject the liquid. However, the high-strength filler or phosphor in the liquid causes wear on the surfaces of the rod and nozzle during the dispensing process. As a result, the ejection reliability decreases as the wear on the surfaces increases. Therefore, it is necessary to estimate the wear characteristics of the rod and nozzle via an experiment and FE analysis. Reliability rests up to 1,000 cycles are conducted under relatively severe conditions. The flow rate and surfaces roughness of the rod and nozzle are measured in each ejection cycle. The surface images and wear volume are obtained before and after the tests and the ejection reliability is confirmed by measuring the flow rate of the liquid. The experimental results show that the ejection reliability is maintained up to 1,000k cycles; these results are validated by the simulation results.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.2
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• pp.89-96
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• 2000

This paper describes the forward type pulse power supply which is the simple circuit configuration and easy to be managed using a power semiconductor switching device(Power-MOSFET) in the view of commercialization. The maximum value of output pulse voltage of the proposed pulse power supply system can be realized by the variation of phase angle($\phi$) of bridge rectifier circuit and also its pulse period is determined by the duty ratio of Power-MOSFET. The principle of basic operating and the operating characteristics of the forward type pulse power supply are estimated by the switching frequency, the variation of phase angle($\phi$)It is shown that theoretical and experimental results are in good agreement by comparing simulation and experimental results of proposed pulse power supply when a lamp type ozonizer can be used as a load. This proposed pulse power system shows that it can be practically used in the future as a power source system in various fields.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.36-42
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• 2016

In multi-level-cell based storage devices, TLC NAND has been employed solid state drive due to cost effectiveness. Since TLC has slow performance and low endurance compared with MLC, TLC based storage has adopted SLC buffer scheme to improve performance. To improve SLC buffer scheme, this paper proposes page overwriting method in SLC block. This method provides data updates without erase operation within a limited number. When SLC buffer area is filled up, FTL should execute copying valid pages and erasing it. The proposed method reduces erase counts by 50% or more compared with previous SLC buffer scheme. Simulation results show that the proposed SLC buffer overwrite method achieves 2 times write performance improvement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.262-271
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• 2011

In this work, we present a unified analytical surface potential model, valid for both PD and FD SOI MOSFETs. Our model is based on a simplified one dimensional and purely analytical approach, and builds upon an existing model, proposed by Yu et al. [4], which is one of the most recent compact analytical surface potential models for SOI MOSFETs available in the literature, to improve its accuracy and remove its inconsistencies, thereby adding to its robustness. The model given by Yu et al. [4] fails entirely in modeling the variation of the front surface potential with respect to the changes in the substrate voltage, which has been corrected in our modified model. Also, [4] produces self-inconsistent results due to misinterpretation of the operating mode of an SOI device. The source of this error has been traced in our work and a criterion has been postulated so as to avoid any such error in future. Additionally, a completely new expression relating the front and back surface potentials of an FD SOI film has been proposed in our model, which unlike other models in the literature, takes into account for the first time in analytical one dimensional modeling of SOI MOSFETs, the contribution of the increasing inversion charge concentration in the silicon film, with increasing gate voltage, in the strong inversion region. With this refinement, the maximum percent error of our model in the prediction of the back surface potential of the SOI film amounts to only 3.8% as compared to an error of about 10% produced by the model of Yu et al. [4], both with respect to MEDICI simulation results.