• Title/Summary/Keyword: semiconductor process

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Modeling and Simulation of Electron-beam Lithography Process for Nano-pattern Designs using ZEP520 Photoresist (ZEP520 포토리지스트를 이용한 나노 패턴 형성을 위한 전자빔 리소그래피 공정 모델링 및 시뮬레이션)

  • Son, Myung-Sik
    • Journal of the Semiconductor & Display Technology
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    • v.6 no.3
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    • pp.25-33
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    • 2007
  • A computationally efficient and accurate Monte Carlo (MC) simulator of electron beam lithography process, which is named SCNU-EBL, has been developed for semiconductor nanometer pattern design and fabrication. The simulator is composed of a MC simulation model of electron trajectory into solid targets, an Gaussian-beam exposure simulation model, and a development simulation model of photoresist using a string model. Especially for the trajectories of incident electrons into the solid targets, the inner-shell electron scattering of an target atom and its discrete energy loss with an incident electron is efficiently modeled for multi-layer resists and heterogeneous multi-layer targets. The simulator was newly applied to the development profile simulation of ZEP520 positive photoresist for NGL(Next-Generation Lithography). The simulation of ZEP520 for electron-beam nanolithography gave a reasonable agreement with the SEM experiments of ZEP520 photoresist.

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Advanced Abnormal Over-current Protection with SuperFET® 800V MOSFET in Flyback converter

  • Jang, KyungOun;Lee, Wontae;Baek, Hyeongseok
    • Proceedings of the KIPE Conference
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    • 2018.07a
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    • pp.332-333
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    • 2018
  • This paper presents an advanced abnormal over-current protection with $SuperFET^{(R)}$ 800V MOSFET in Flyback converter. In advanced abnormal over-current protection, digital pattern generator is proposed to detect a steep di/dt current condition when secondary rectifier diode or the transformer is shorted. If current sensing signal is larger than current limit during consecutive switching cycle, Gate signal will be stopped for 7 internal switching periods. If the abnormal over-current maintains pattern, the controller goes into protection mode. The Advanced over-current protection has been implemented in a 0.35um BCDMOS process (ON Semiconductor process).

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Laser Processing Technology in Semiconductor and Display Industry (반도체 및 디스플레이 산업에서의 레이저 가공 기술)

  • Cho, Kwang-Woo;Park, Hong-Jin
    • Journal of the Korean Society for Precision Engineering
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    • v.27 no.6
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    • pp.32-38
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    • 2010
  • Laser material processing technology is adopted in several industry as alternative process which could overcome weakness and problems of present adopted process, especially semiconductor and display industry. In semiconductor industry, laser photo lithography is doing at front-end level, and cutting, drilling, and marking technology for both wafer and EMC mold package is adopted. Laser cleaning and de-flashing are new rising technology. There are 3 kinds of main display industry which use laser technology - TFT LCD, AMOLED, Touch screen. Laser glass cutting, laser marking, laser direct patterning, laser annealing, laser repairing, laser frit sealing are major application in display industry.

A Study on Temperature Characteristics according to Ceramic Material Stacking Sequence of Electrostatic Chuck Surface (정전척 표면의 세라믹물질 적층 순서에 따른 온도 특성에 관한 연구)

  • Jang, Kyungmin;kim, Kwangsun
    • Journal of the Semiconductor & Display Technology
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    • v.16 no.3
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    • pp.116-120
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    • 2017
  • Temperature uniformity of a wafer in a semiconductor process is a very important factor that determines the overall yield. Therefore, it is very important to confirm the temperature characteristics of the chuck surface on which the wafer is lifted. The temperature characteristics of the chuck depend on the external heat source, the shape of the cooling channel inside the chuck, the material on the chuck surface, and so on. In this study, CFD confirms the change of temperature characteristics according to the stacking order of ceramic materials on the chuck surface, and suggests the best lamination method.

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Topology Optimization of Reinforcement Pattern for Pressure-Explosion Proof Enclosure Door in Semiconductor Manufacturing Process (위상최적화 기법을 이용한 반도체 공정용 압력방폭형 외함 도어의 보강 패턴 최적화)

  • Yeong Sang Kim;Dong Seok Shin;Euy Sik Jeon
    • Journal of the Semiconductor & Display Technology
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    • v.22 no.2
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    • pp.56-63
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    • 2023
  • This paper presents a method using finite element analysis and topology optimization to address the issue of overdesign in pressure-explosion proof enclosure doors for semiconductor manufacturing processes. The design conducted in this paper focuses on the pattern design of the enclosure door and its fixation components. The process consists of a solid-filled model, a topology optimization model, and a post-processing model. By applying environmental conditions to each model and comparing the maximum displacement, maximum equivalent stress, and weight values, it was confirmed that a reduction of about 13% in weight is achievable.

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W Polymetal Gate Technology for Giga Bit DRAM

  • Jung, Jong-Wan;Han, Sang-Beom;Lee, Kyungho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.1
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    • pp.31-39
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    • 2001
  • W polymetal gate technology for giga bit DRAM are presented. Key module processes for polymetal gate are studied in detail. $W/WN_x/poly-silicon$ adopted for a word line of 256Mbit DRAM has good gate oxide integrity and junction leakage characteristics through full integration, which is comparable to those of conventional $WSi_x$/Poly-silicon gate process. These results undoubtedly show that $W/WN_x/poly-silicon$ is the strongest candidate as a word line for Giga bit DRAM.

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Studies on Flip Chip Underfill Process by using Molding System (몰딩공정을 응용한 플립칩 언더필 연구)

  • 한세진;정철화;차재원;서화일;김광선
    • Journal of the Semiconductor & Display Technology
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    • v.1 no.1
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    • pp.29-33
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    • 2002
  • In the flip-chip process, the problem like electric defect or fatigue crack caused by the difference of CTE, between chip and substrate board had occurred. Underfill of flip chip to overcome this defects is noticed as important work developing in whole reliability of chip by protecting the chip against the external shock. In this paper, we introduce the underfill methods using mold and plunge and improvement of process and reliability, and the advantage which can be taken from embodiment of device.

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A Foresight Study on Strategy of Semiconductor Memory Industry by Performance Analysis of Semiconductor Industry (반도체 산업의 성과 분석을 통한 메모리 산업의 미래 전략 도출)

  • Chung, Euiyoung
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.11 no.4
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    • pp.1-12
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    • 2015
  • This research analyzes the current state of the semiconductor industry delivering the prediction for the future development of the semiconductor industry along with some semiconductor memory's responsive strategies. In the 2014, top 10 semiconductor companies were targeted and studied its growth based on its profitability and growth indications in perspective during three years. The system semiconductor industry with the increase in Hyper-scale customers, proactive actions in the technology consortium, is polarizing caused by increased R&D expense to ensure process scaling limits and high performance, and some results have shown: PC and Mobile slowdown and growth recession phenomenon due to IoT's unclear direction. The leading company is to secure new growth engines through 'Acquiring'. While as the subordinated companies following this consecutive survival through the 'Acquired', the future of system semiconductor industry is to strengthen the market dominance and its techniques by concentrating on the reorganization of the market by few large companies. Accordingly, the semiconductor memory industry is expected to reach the limit of its expansion to domain of system semiconductor, and it is highly suggesting the need of the 'Memory Life Extension' growth strategy.

Applying a Life-Cycle Assessment to the Ultra Pure Water Process of Semiconductor Manufacturing

  • Tien, Shiaw-Wen;Chung, Yi-Chan;Tsai, Chih-Hung;Yang, Yung-Kuang;Wu, Min-Chi
    • International Journal of Quality Innovation
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    • v.6 no.3
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    • pp.173-189
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    • 2005
  • A life-cycle assessment (LCA) is based on the attention given to the environmental protection and concerning the possible impact while producing, making, and consuming products. It includes all environmental concerns and the potential impact of a product's life cycle from raw material procurement, manufacturing, usage, and disposal (that is, from cradle to grave). This study assesses the environmental impact of the ultra pure water process of semiconductor manufacturing by a life-cycle assessment in order to point out the heavy environmental impact process for industry when attempting a balanced point between production and environmental protection. The main purpose of this research is studying the development and application of this technology by setting the ultra pure water of semiconductor manufacturing as a target. We evaluate the environmental impact of the Precoat filter process and the Cation/Anion (C/A) filter process of an ultra pure water manufacturing process. The difference is filter material used produces different water quality and waste material, and has a significant, different environmental influence. Finally, we calculate the cost by engineering economics so as to analyze deeply the minimized environmental impact and suitable process that can be accepted by industry. The structure of this study is mainly combined with a life-cycle assessment by implementing analysis software, using SimaPro as a tool. We clearly understand the environmental impact of ultra pure water of semiconductor used and provide a promotion alternative to the heavy environmental impact items by calculating the environmental impact during a life cycle. At the same time, we specify the cost of reducing the environmental impact by a life-cycle cost analysis.