• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.4
• /
• pp.17-22
• /
• 2000

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

• Journal of the Microelectronics and Packaging Society
• /
• v.6 no.2
• /
• pp.31-36
• /
• 1999

An efficient method for thermal modeling of QFP is Proposed. Thermal measurement data are given to verify the method. In parallel with the experiment, an exact full 3-D model calculation is also provided. One fonds that there is an excellent agreement between validation data and the efficient model data.

• Journal of the Microelectronics and Packaging Society
• /
• v.18 no.2
• /
• pp.35-41
• /
• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.10a
• /
• pp.131-175
• /
• 2000

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2007.04a
• /
• pp.67-79
• /
• 2007

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.11a
• /
• pp.43-46
• /
• 2000

• Journal of the Microelectronics and Packaging Society
• /
• v.30 no.3
• /
• pp.11-19
• /
• 2023

Recently with the rapid advancement of artificial intelligence (AI) technologies such as Chat GPT, AI semiconductors have become important. AI technologies require the ability to process large volumes of data quickly, as they perform tasks such as big data processing, deep learning, and algorithms. However, AI semiconductors encounter challenges with excessive power consumption and data bottlenecks during the processing of large-scale data. Thus, the latest packaging technologies are required for AI semiconductor computations. In this study, the authors have described packaging technologies applicable to AI semiconductors, including interposers, Through-Silicon-Via (TSV), bumping, Chiplet, and hybrid bonding. These technologies are expected to contribute to enhance the power efficiency and processing speed of AI semiconductors.

• Journal of the Semiconductor & Display Technology
• /
• v.12 no.1
• /
• pp.23-28
• /
• 2013

Epoxy resins are widely used in microelectronics packaging such as printed circuit board and encapsulating for semiconductor manufacturing. Water can diffuse into and through the epoxy matrix systems and moisture absorption at boarding interfaces of matrix resin systems can lead to a hydrolysis at the interfaces resulting in delamination of encapsulating materials. In the study, the changes of diffusion coefficient and moisture content ratio of epoxy resin systems with nano-sized fillers according to the change of liquid type epoxy resins were investigated. RE-304S, RE-310S, RE-810NM and HP-4032D as a epoxy resin, Kayahard AA as a hardener, and 1B2MI as a catalyst were used in these epoxy resin systems. After curing, moisture content ratios were measured with time under the 85 and 85% relative humidity condition using a thermo-hydrostat. The maximum moisture absorption ratio and diffusion coefficient of EMC decrease with the filler content. It can be seen that these decreases are due to the increase of filler surface area and the decrease of moisture through channel with the content of nano-sized filler.

• Proceedings of the KAIS Fall Conference
• /
• 2002.11a
• /
• pp.278-282
• /
• 2002

This study is object to semiconductor cavity block production technology using CAD/CAM. Semiconductor packaging is require to the high intensity, high temperature and good metals. That raw metals name is ASP23 and high price. This results are propose to one direction of semiconductor cavity block production technology.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.4
• /
• pp.35-39
• /
• 2013

A four point bending apparatus has been developed to measure semiconductor sensor piezoresistance inside a four inch probe station. The apparatus has a footprint of $60{\times}83mm^2$ and can apply $10{\mu}m$ displacements using a vertical micrometer stage. We used finite element analysis to predict and improve the accuracy of the instrument. Finally strain gauge attached on a silicon test piece was used to experimentally verify the setup.