• 제목/요약/키워드: semiconductor manufacturing process

검색결과 571건 처리시간 0.024초

시뮬레이션과 AHP/DEA를 이용한 반도체 부품 생산라인 개선안 결정 (Determination of New Layout in a Semiconductor Packaging Substrate Line using Simulation and AHP/DEA)

  • 김동수;박철순;문덕희
    • 산업공학
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    • 제25권2호
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    • pp.264-275
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    • 2012
  • The process of semiconductor(IC Package) manufacturing usually includes lots of complex and sequential processes. Many kinds of equipments are installed with the mixed concept of serial and parallel manufacturing system. The business environments of the semiconductor industry have been changed frequently, because new technologies are developed continuously. It is the main reason of new investment plan and layout consideration. However, it is difficult to change the layout after installation, because the major equipments are expensive and difficult to move. Furthermore, it is usually a multiple-objective problem. Thus, new investment or layout change should be carefully considered when the production environments likewise product mix and production quantity are changed. This paper introduces a simulation case study of a Korean company that produces packaging substrates(especially lead frames) and requires multi-objective decision support. $QUEST^{(R)}$ is used for simulation modelling and AHP(Analytic Hierarchy Process) and DEA(Data Envelopment Analysis) are used for weighting of qualitative performance measures and solving multiple-objective layout problem, respectively.

제조시스템자동화에 있어서 BPEL 기반 워크플로우 관리시스템의 적용 (The Implementation of BPEL based Workflow Management System in Manufacturing System Automation)

  • 박동진;;장병훈;김수경
    • 한국IT서비스학회:학술대회논문집
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    • 한국IT서비스학회 2009년도 춘계학술대회
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    • pp.270-276
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    • 2009
  • This paper outlines opportunities and challenges in the Implementation of BPEL based WFMS(Work Flow Management System) for the MES(Manufacturing Execution Systems) level in semiconductor manufacturing. At present, the most MES that are composed of several hundreds of applications in semiconductor wafer fabrication shop have the same problems as others about flexibility and adaptability. When a plant has to produce new product mix, remodel the manufacturing execution process, or replace obsolete equipments, the principal road blocks for responding to new manufacturing environment are inflexible communication infrastructure among the manufacturing process components and the difficulty in porting existing application software to new configurations. In this paper, the issues about BPEL standard, used for the flexibility of Workflow Management System, are presented. We introduce the integrated development framework named nanoFlow which is optimized for developing the BPEL based WFMS application for automated manufacturing system. We describe a WFMS implemented with using nanoFlow framework, review and evaluate the system in terms of flexibility and adaptability.

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반도체 공정에서의 Wafer Map Image 분석 방법론 (Wafer Map Image Analysis Methods in Semiconductor Manufacturing System)

  • 유영지;안대웅;박승환;백준걸
    • 대한산업공학회지
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    • 제41권3호
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    • pp.267-274
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    • 2015
  • In the semiconductor manufacturing post-FAB process, predicting a package test result accurately in the wafer testing phase is a key element to ensure the competitiveness of companies. The prediction of package test can reduce unnecessary inspection time and expense. However, an analysing method is not sufficient to analyze data collected at wafer testing phase. Therefore, many companies have been using a summary information such as a mean, weighted sum and variance, and the summarized data reduces a prediction accuracy. In the paper, we propose an analysis method for Wafer Map Image collected at wafer testing process and conduct an experiment using real data.

Array Testing of TFT-LCD Panel with Integrated Gate Driver Circuits

  • Lee, Jonghwan
    • 반도체디스플레이기술학회지
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    • 제19권3호
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    • pp.68-72
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    • 2020
  • A new method for array testing of TFT-CD panel with the integrated gate driver circuits is presented. As larger size/high resolution TFT-LCD with the peripheral driver circuits has emerged, one of the important problems for manufacturing is array testing on the panel. This paper describes the technology of detecting defective arrays and optimizing the array testing process. For the effective characterization of pixel array, the pixel storage capability is simulated and measured with voltage imaging system. This technology permits full functional testing during the manufacturing process, enabling fabrication of large TFT-LCD panels with the integrated driver circuits.

SSVM(Stepwise-Support Vector Machine)을 이용한 반도체 수율 예측 (A Yields Prediction in the Semiconductor Manufacturing Process Using Stepwise Support Vector Machine)

  • 안대웅;고효헌;김지현;백준걸;김성식
    • 산업공학
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    • 제22권3호
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    • pp.252-262
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    • 2009
  • It is crucial to prevent low yields in the semiconductor industry. Since many factors affect variation in yield and they are deeply related, preventing low yield is difficult. There have been substantial researches in the field of yield prediction. Many researchers had used the statistical methods. Many studies have shown that artificial neural network (ANN) achieved better performance than traditional statistical methods. However, despite ANN's superior performance some problems such as over-fitting and poor explanatory power arise. In order to overcome these limitations, a relatively new machine learning technique, support vector machine (SVM), is introduced to classify the yield. SVM is simple enough to be analyzed mathematically, and it leads to high performances in practical applications. This study presents a new efficient classification methodology, Stepwise-SVM (SSVM), for detecting high and low yields. SSVM is step-by-step adjustment of parameters to be precisely the classification for actual high and low yield lot. The objective of this paper is to examine the feasibility of SVM and SSVM in the yield classification. The experimental results show that SVM and SSVM provides a promising alternative to yield classification for the field data.

Abnormal Detection in 3D-NAND Dielectrics Deposition Equipment Using Photo Diagnostic Sensor

  • Kang, Dae Won;Baek, Jae Keun;Hong, Sang Jeen
    • 반도체디스플레이기술학회지
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    • 제21권2호
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    • pp.74-84
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    • 2022
  • As the semiconductor industry develops, the difficulty of newly required process technology becomes difficult, and the importance of production yield and product reliability increases. As an effort to minimize yield loss in the manufacturing process, interests in the process defect process for facility diagnosis and defect identification are continuously increasing. This research observed the plasma condition changes in the multi oxide/nitride layer deposition (MOLD) process, which is one of the 3D-NAND manufacturing processes through optical emission spectroscopy (OES) and monitored the result of whether the change in plasma characteristics generated in repeated deposition of oxide film and nitride film could directly affect the film. Based on these results, it was confirmed that if a change over a certain period occurs, a change in the plasma characteristics was detected. The change may affect the quality of oxide film, such as the film thickness as well as the interfacial surface roughness when the oxide and nitride thin film deposited by plasma enhenced chemical vapor deposition (PECVD) method.

적응 훈련 신경망을 이용한 플라즈마 식각 공정 수율 향상을 위한 공정 분석 및예측 시스템 개발 (Development of Process Analysis and Prediction Systeme to Improve Yield in Plasma Etching Process Using Adaptively Trained Neural Network)

  • 최문규;김훈모
    • 한국정밀공학회지
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    • 제16권11호
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    • pp.98-105
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    • 1999
  • As the IC(Integrated Circuit) has been densified and complicated, it is required to thorough process control to improve yield. Experts, for this purpose, focused on the process analysis automation, which is came from the strict data management in semiconductor manufacturing. In this paper, we presents the process analysis system that can analyze causes, for a output after processes. Also, the plasma etching process that highly affects yield among semiconductor process is modeled to predict a output before the process. To approach this problem, we use adaptively trained neural networks that exhibit superior accuracy over statistical techniques. And in comparison with methods in other paper, a method that history of trend for input data is considered is shown to offer advantage in both learning and prediction capability. This research regards CD(Critical Dimension) that is considerable in high integrated circuit as output variable of the prediction model.

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제조실행시스템에서의 BPEL 기반 워크플로우 관리시스템의 적용 (Implementation of BPEL based Workflow Management System in Manufacturing Execution Systems)

  • 박동진;장병훈
    • 한국IT서비스학회지
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    • 제8권4호
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    • pp.165-174
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    • 2009
  • This paper outlines opportunities and challenges in the implementation of BPEL based WFMS(WorkFlow Management System) for the MES(Manufacturing Execution Systems) in semiconductor manufacturing. At present, the most MESs in semiconductor wafer fabrication shop have the problems in terms of application software integration, reactivity, and adaptability. When a plant has to produce new product mix, remodel the manufacturing execution process, or replace obsolete equipments, the principal road blocks for responding to new manufacturing environment are the difficulties in porting existing application software to new configurations. In this paper, the issues about WFMS technologies including BPEL standard applied for MES are presented. And then, we introduce the integrated development framework named nanoFlow which is optimized for developing the BPEL based WFMS application for automated manufacturing system. And we describe a WFMS implemented with using nanoFlow framework, review and evaluate the system.

An Evaluation of Multiple-input Dual-output Run-to-Run Control Scheme for Semiconductor Manufacturing

  • Fan, Shu-Kai-S.;Lin, Yen
    • Industrial Engineering and Management Systems
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    • 제4권1호
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    • pp.54-67
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    • 2005
  • This paper provides an evaluation of an optimization-based, multiple-input double-output (MIDO) run-to-run (R2R) control scheme for general semiconductor manufacturing processes. The controller in this research, termed adaptive dual response optimizing controller (ADROC), can serve as a process optimizer as well as a recipe regulator between consecutive runs of wafer fabrication. In evaluation, it is assumed that the equipment model could be appropriately described by a pair of second-order polynomial functions in terms of a set of controllable variables. Of practical relevance is to consider a drifting effect in the equipment model since in common semiconductor practice the process tends to drift due to machine aging and tool wearing. We select a typical application of R2R control to chemical mechanical planarization (CMP) in semiconductor manufacturing in this evaluation, and there are five different CMP process scenarios demonstrated, including mean shift, variance increase, and IMA disturbances. For the controller, ADROC, an on-line estimation technique is implemented in a self-tuning (ST) control manner for the adaptation purpose. Subsequently, an ad hoc global optimization algorithm based on the dual response approach, arising from the response surface methodology (RSM) literature, is used to seek the optimum recipe within the acceptability region for the execution of next run. The main components of ADROC are described and its control performance is assessed. It reveals from the evaluation that ADROC can provide excellent control actions for the MIDO R2R situations even though the process exhibits complicated, nonlinear interaction effects between control variables, and the drifting disturbances.

AHP를 활용한 반도체부품 생산공정 시뮬레이션 연구 (A Simulation Study on the Manufacturing Process of Semiconductor Parts Using AHP)

  • 허특;문덕희;박철순;장병림
    • 한국시뮬레이션학회논문지
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    • 제18권2호
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    • pp.65-75
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    • 2009
  • 반도체 생산공정은 다양한 장비들이 복잡하게 서로 연관된 일련의 작업들로 구성되어 있다. 이들 장비들은 공학적 또는 환경적 요인들을 고려하여 직렬 또는 병렬의 혼합구조로 배치되어 있다. 따라서 많은 비용이 발생하고, 동시에 고려해야할 사항이 복잡하므로 한 번 설치되면 레이아웃 변경이 거의 불가능한 실정이다. 따라서 생산량의 변동이나 신제품의 개발과 같은 상황에서 새로운 설비의 투자나 레이아웃의 변경은 매우 신중하게 결정되어야 한다. 본 논문은 반도체의 부품을 생산하는 공장에 대해 시뮬레이션을 적용한 사례연구다. 시뮬레이션 모델은 $QUEST^{(R)}$라는 도구를 이용하여 개발되었으며, 시뮬레이션을 통하여 생산환경의 변화에 대응하는 다양한 전략을 검토하였다. 또한 본 연구에서는 결정인자가 다수인 대안에서 최적안을 도출해 내기 위하여 AHP 기법을 사용하였다.