• 제목/요약/키워드: semiconductor laser

검색결과 525건 처리시간 0.027초

2상(相)8극영구자석형(極永久磁石形) LPM의 자기회로설계(磁氣回路設計)와 제어방식(制御方式)에 관한 연구(硏究) (A Study on the Magnetic Circuit Design and Control Method of 2-Phase 8-Pole PM Type Linear Pulse Motor)

  • 김일중;이은웅;이민명;이명일
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1991년도 하계학술대회 논문집
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    • pp.47-50
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    • 1991
  • LPM(Linear Pulse Motor) provide direct and precise position control of bidirectional linear motion. LPM is not subject to the same linear velocity and acceleration limitations inherent in systems converting rotary to linear motion such as lead screws, rack and pinion, belt and pulley drives. With LPM, all the thrust force generated by the motor is efficiently applied directly to the load. And speed, distance, and acceleration are easily programmed in a highly repeatable fashion. Potential industrial and application fields of LPM include PCB assembly, industrial sewing machines, automatic inspection, coil winder, medical uses, conveyer system, laser cut and trim systems, semiconductor wafer processing, OA instruments etc. This paper describes various design parameter of LPM such as magnetic ciucuit construction methods, phase number and tooth number per pole, permanent magnet and coil mmf, tooth geometries. And to solve the problems of existing control methods, in this paper, a new control method of the LPM is proposed throughout modern control theory.

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액체호닝에 의한 금형 자동 사상기계개발 및 가공 특성 (Polishing Characteristics and Development of Automatic Die Polishing Machine by Liquid Honing)

  • 김재도;류기덕;홍정석
    • 한국정밀공학회지
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    • 제17권6호
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    • pp.162-168
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    • 2000
  • The automatic die polishing machine by liquid honing has been developed and experimented on the surface of machined die. The goal of development in the automatic die polishing machine by liquid honing is to increase the accuracy and the productivity in die polishing. To reach this goal, the polishing machine consists of the automatic measuring device for contour of die, the nozzle and pumping system to spray the powder mixed with liquid, and the 3-axis guides. Before polishing, the measuring device with a semiconductor laser scans the surface of mould to get the data of contour. The data store a PC and use to control the nozzle head to move above a couple of centimeters on the machined surface of die. The experimental parameters are the spraying time, the pressure, the size of abrasive grain and the mixing ratio between abrasive grain and liquid. The surface roughness is measured on the polished die which are SKDl 1 and Al7075 machined by NC. The surface roughness indicates the values of Rmax 0.5${\mu}{\textrm}{m}$ for Al7075 and Rmax 1.4${\mu}{\textrm}{m}$ for SKDl 1. It reduces the polishing time significantly and reduces the monotonous work for labors. As the results, the liquid honing system is useful method to apply for the die polishing and the automatic die polishing machine using liquid honing shows that it's very effective processing ability.

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Controllability of Structural, Optical and Electrical Properties of Ga doped ZnO Nanowires Synthesized by Physical Vapor Deposition

  • Lee, Sang Yeol
    • Transactions on Electrical and Electronic Materials
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    • 제14권3호
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    • pp.148-151
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    • 2013
  • The control of Ga doping in ZnO nanowires (NWs) by physical vapor deposition has been implemented and characterized. Various Ga-doped ZnO NWs were grown using the vapor-liquid-solid (VLS) method, with Au catalyst on c-plane sapphire substrate by hot-walled pulsed laser deposition (HW-PLD), one of the physical vapor deposition methods. The structural, optical and electrical properties of Ga-doped ZnO NWs have been systematically analyzed, by changing Ga concentration in ZnO NWs. We observed stacking faults and different crystalline directions caused by increasing Ga concentration in ZnO NWs, using SEM and HR-TEM. A $D^0X$ peak in the PL spectra of Ga doped ZnO NWs that is sharper than that of pure ZnO NWs has been clearly observed, which indicated the substitution of Ga for Zn. The electrical properties of controlled Ga-doped ZnO NWs have been measured, and show that the conductance of ZnO NWs increased up to 3 wt% Ga doping. However, the conductance of 5 wt% Ga doped ZnO NWs decreased, because the mean free path was decreased, according to the increase of carrier concentration. This control of the structural, optical and electrical properties of ZnO NWs by doping, could provide the possibility of the fabrication of various nanowire based electronic devices, such as nano-FETs, nano-inverters, nano-logic circuits and customized nano-sensors.

기판에 의한 응력과 입계크기가 이산화바나듐 박막 형성에 미치는 영향 연구 (Effect of Substrate-Induced Stress and Grain Size on the formation of VO2 thin films)

  • 구현;배성환;신동민;권오정;박찬
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.1279_1280
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    • 2009
  • Vanadium dioxide(VO2) has been reported to be the most attractive material for thermochromic windows due to its semiconductor-metal phase transition at around $68^{\circ}C$. However, our previous experiment showed it is difficult to grow VO2 thin films directly on glass substrate, whereas thermochromic VO2 thin films were successfully grown on R-cut sapphire substrate. Properties of VO2 thin films on different orientations of sapphire substrates were already reported. Furthermore, VO2 thin films were successfully grown heteroepitaxially on (001) preferred oriented ZnO coated glass. We deposited VO2 thin films using V2O5 targets on substrates with various lattice parameters with same orientation(SrTiO3, MgO, and Sapphire substrate of (001) orientation) by pulsed laser deposition. In this work, we will discuss the effects of lattice misfit, substrate-induced stress and grain size on the properties of VO2 thin films deposited on various substrate materials.

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반도체 웨이퍼의 스트레스 측정을 위한 공정 및 표면 검사시스템 구현 (Implementation of process and surface inspection system for semiconductor wafer stress measurement)

  • 조태익;오도창
    • 대한전자공학회논문지SD
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    • 제45권8호
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    • pp.11-16
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    • 2008
  • 본 논문에서는 먼저 RTP(Rapid Thermal Processor) 장치를 스트레스 측정에 용이한 구조로 제작하고 PC에서 통합 공정관리 시스템을 설계하였다. 다음으로는 Large deformation 이론을 바탕으로 반도체 웨이퍼 표면의 변형검사를 위한 레이져 인터페로미터리를 구성하였다. 궁극적으로 이러한 레이져장치로부터 웨이퍼 표면의 영상을 추출하고 세선화, 블록화 그리고 스트레스 분포도의 순서로 영상처리 하여 스트레스로 인한 웨이퍼 표면의 변형을 검사하였다. 실험을 하기 위해 변형이 이루어지도록 웨이퍼의 후면을 1mm정도 갈아낸 후 약 1000도에서 $3\sim4$회 열처리를 수행하였으며, 열처리를 가한 영상과 가하지 않은 영상을 통하여 웨이퍼 열처리 후 심각한 변형이 이루어졌음을 알 수 있었다.

초고속 OTDM/WDM을 위한 파장 및 반복율 가변 광 펄스 발생 (Wavelength and Repetition-Rate Tunable Optical Pulse Generation for Ultrafast OTDM/WDM)

  • 최경선;한종민;서동선;전영민;이석
    • 전기전자학회논문지
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    • 제5권2호
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    • pp.201-210
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    • 2001
  • 광 시분할 및 파장분할 다중화에 의한 초고속 광통신 시스템에 적합한 파장 및 반복율 가변 능력을 갖는 초단 펄스열을 고리형 반도체 광섬유 레이저의 광주입 모드잠김에 의해 발생시켰다. 발생된 광 펄스열은 10 GHz, 20 GHz, 30 GHz, 및 40 GHz의 다양한 반복율에서 ${\sim}10$ 피코초 정도의 펄스폭과 30 nm가 넘는 파장 가변능력을 보였다.

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Hot Plate 신뢰성 시험.평가장비 개발 (Reliability Evaluation System of Hot Plate for PR Baking)

  • 송준엽;송창규;노승국;박화영
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2001년도 춘계학술대회 논문집
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    • pp.566-569
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    • 2001
  • Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist(PR) and to bake coated PR in FAB process of semiconductor. It is necessary to guarantee the performance of Hot Plate(HP). Therefore, in this study designed and developed the reliability system of HP to measure and estimated thermal uniformity and flatness in temperature setting amplitude $0~250^{\circ}C$. We developed the techniques that measures and analyzes thermal uniformity using infrared thermal vision, and compensates measuring error of flatness using laser displacement sensor. For measuring flatness, we specially makes the measurement stage of 3 axes which adopts the precision encoder. The allowable error of measuring technique is less than thermal uniformity, $\pm 0.1^{\circ}C$ and flatness, $\pm 1mm$. It is expected that the developed system can measure from $\Phi$210(wafer 8") to $\Phi$356(wafer 12") and also can be used in performance test of the Cool Plate and industrial heater, etc.

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A Trapping Behavior of GaN on Diamond HEMTs for Next Generation 5G Base Station and SSPA Radar Application

  • Lee, Won Sang;Kim, John;Lee, Kyung-Won;Jin, Hyung-Suk;Kim, Sang-Keun;Kang, Youn-Duk;Na, Hyung-Gi
    • International Journal of Internet, Broadcasting and Communication
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    • 제12권2호
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    • pp.30-36
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    • 2020
  • We demonstrated a successful fabrication of 4" Gallium Nitride (GaN)/Diamond High Electron Mobility Transistors (HEMTs) incorporated with Inner Slot Via Hole process. We made in manufacturing technology of 4" GaN/Diamond HEMT wafers in a compound semiconductor foundry since reported [1]. Wafer thickness uniformity and wafer flatness of starting GaN/Diamond wafers have improved greatly, which contributed to improved processing yield. By optimizing Laser drilling techniques, we successfully demonstrated a through-substrate-via process, which is last hurdle in GaN/Diamond manufacturing technology. To fully exploit Diamond's superior thermal property for GaN HEMT devices, we include Aluminum Nitride (AlN) barrier in epitaxial layer structure, in addition to conventional Aluminum Gallium Nitride (AlGaN) barrier layer. The current collapse revealed very stable up to Vds = 90 V. The trapping behaviors were measured Emission Microscope (EMMI). The traps are located in interface between Silicon Nitride (SiN) passivation layer and GaN cap layer.

칼코게나이드 박막의 전기적 펄스에 의한 상변화 연구 (The phase transition with electric field in chalcogenide thin films)

  • 양성준;신경;이재민;정홍배
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 춘계학술대회 논문집 디스플레이 광소자분야
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    • pp.115-118
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    • 2004
  • The phase transition between amorphous and crystalline states in chalcogenide semiconductor films can controlled by electric pulses or pulsed laser beam; hence some chalcogenide semoconductor films can be applied to electrically write/erase nonvolatile memory devices, where the low conductive amorphous state and the high conductive crystalline stale are assigned to binary states. AST(AsSbTe) used to phase change material by applying electical pulses. Thickness of AST chalcogenide thin film have about 100nm. Electrodes are made of ITO and Al. $T_c$(Crystallization temperature) of AST system is lower than that of the GST(GeSbTe) system, so that the current pulse width of crystallization process can be decreased.

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Silicon 기반 IC 디바이스에서의 층간 절연막 특성 분석 연구 (Raman Spectroscopy Analysis of Inter Metallic Dielectric Characteristics in IC Device)

  • 권순형;표성규
    • 마이크로전자및패키징학회지
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    • 제23권4호
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    • pp.19-24
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    • 2016
  • Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.