• 한국산학기술학회논문지
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• 제18권6호
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• pp.37-43
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• 2017

본 논문에서는 고출력 전자기파 (Electromagnetic pulses, EMP) 영향에 의해 발생하는 반도체 부품의 물리적 상호작용에 대한 원리와 고장 발생 메커니즘의 연구를 위해 선행된 연구 내용을 고찰하였다. 반도체 부품에서의 전자기파 전이 과정은 3층 (공기/유전체/도체) 구조로 설명할 수 있으며, 복소반사계수에 의하여 이론적으로 흡수되는 에너지를 예상할 수 있다. 반도체 부품에 전달된 과도한 고출력 전자기파로 인한 반도체 부품의 주요 고장 원인은 전자기파 커플링에 의한 부품 소재의 줄 열에너지의 발생이다. 전기장에 의한 유전가열과 자기장에 의한 맴돌이손실에 의해 반도체 칩의 P-N 접합 파괴, 회로패턴의 burn-out과 리드 프레임과 칩을 연결하는 와이어의 손상 등이 발생한다. 즉, 반도체 부품에 전달된 전자기파는 반도체 내부 물질과 상호작용을 하며, 쌍극자분극과 이온 전도도 현상이 동시에 발생하여, 칩 내부의 P-N 접합 부분에 과도한 역전압이 형성되어 P-N 접합 파괴를 유발한다. 향후 고 신뢰성을 요구하는 전기전자시스템에 대한 EMP 내성을 향상하기 위한 반도체 부품 수준의 연구가 필요하다.

• 한국전기전자재료학회논문지
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• 제32권5호
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• pp.371-375
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• 2019

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a $SiO_2/Si_3N_4$ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.

• 반도체디스플레이기술학회지
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• 제19권4호
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• pp.6-10
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• 2020

The silver nanowires (AgNWs) were synthesized by the conventional polyol process, which revealed 25 ㎛ and 30 nm of average length and diameter, respectively. The synthesized AgNWs were applied to the CdSe/CdZnS quantum dot (QD) based transparent light-emitting device (LED). The device using a randomly networked AgNWs electrode had some problems such as the high threshold voltage (for operating the device) due to the random pores from the networked AgNWs. As a method of improvement, a composite electrode was formed by overlaying the ZnO:Ga on the AgNWs network. The device used the composite electrode revealed a low threshold voltage (4.4 Vth) and high current density compared to the AgNWs only electrode device. The brightness and current density of the device using composite electrode were 55.57 cd/㎡ and 41.54 mA/㎠ at the operating voltage of 12.8 V, respectively, while the brightness and current density of the device using (single) AgNWs only were 1.71 cd/㎡ and 2.05 mA/㎠ at the same operating voltage. The transmittance of the device revealed 65 % in a range of visible light. Besides the reliability of the devices was confirmed that the device using the composite electrode revealed 2 times longer lifetime than that of the AgNWs only electrode device.

• 반도체디스플레이기술학회지
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• 제21권2호
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• pp.11-14
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• 2022

In this work, we evaluated the Al₂O₃ film, which was deposited by atomic layer deposition, degraded by exposure to harsh environments. The Al₂O₃ films deposited by atomic layer deposition have long been used as a gas diffusion barrier that satisfies barrier requirements for device reliability. To investigate the barrier and mechanical performance of the Al₂O₃ film with increasing temperature and relative humidity, the properties of the degraded Al₂O₃ film exposed to the harsh environment were evaluated using electrical calcium test and tensile test. As a result, the water vapor transmission rate of Al₂O₃ films stored in harsh environments has fallen to a level that is difficult to utilize as a barrier film. Through water vapor transmission rate measurements, it can be seen that the water vapor transmission rate changes can be significant, and the environment-induced degradation is fatal to the Al₂O₃ thin films. In addition, the surface roughness and porosity of the degraded Al₂O₃ are significantly increased as the environment becomes severer. the degradation of elongation is caused by the stress concentration at valleys of rough surface and pores generated by the harsh environment. Becaused the harsh envronment-induced degradation convert amorphous Al₂O₃ to crystalline structure, these encapsulation properties of the Al₂O₃ film was easily degraded.

• 반도체디스플레이기술학회지
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• 제1권1호
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• pp.1-7
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• 2002

Modem technology depends on the reliability of extremely high precision equipments. In the production of semiconductor wafer, optical and electron microscopes, ion-beam, laser device must maintain their alignments within a sub-micrometer. This equipment requires a vibration free environment to provide its proper function. Therefore, this high technology equipments require very strict environmental vibration criteria because it is used as basic data for the design of building structure and structural dynamics of equipment. In this paper, the new approach is proposed to investigate the mismatch problem of time and frequency domain for vibration criteria of sensitive equipment. The proposed approach is based on a vibration measurement data and a relative transfer function which can be obtained by experiment or analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1990년도 추계학술대회 논문집 학회본부
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• pp.263-266
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• 1990

In order to high-respone and high-reliability of devices, it depended upon how we can increase the high-frequency of the Inverter, UPS and it's application. but using high-frequency of self turn-off devices, it is important to reduce switching device loss and spike voltage of turn off. This paper proposed new methode about computer simulation of device loss also experimental results with switching device characteristic are presented.

• International Journal of Quality Innovation
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• 제8권1호
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• pp.137-153
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• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• 대한전자공학회논문지SD
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• 제43권3호
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• pp.1-8
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• 2006

본 논문에서는 채널 stress에 따른 Nano-scale CMOSFET의 소자 및 신뢰성 (HCI, NBTI)특성을 분석하였다. 잘 알려져 있듯이 NMOS는 tensile, PMOS는 compressive stress가 인가된 경우에 소자의 특성이 개선되었으며, 이는 전자와 정공의 이동도 증가에 의한 것임을 확인하였다. 그러나 신뢰성인 경우에는 소자 특성과는 다른 특성을 나타냈는데, NMOS와 PMOS 모두 tensile stress가 인가된 경우에 hot carrier 특성이 더 열화 되었으며, PMOS의 PBTI 특성도 tensile에서 더 열화 되었음을 확인하였다. 신뢰성을 분석한 결과, 채널의 tensile stress로 인하여 $Si/SiO_2$ 계면에서 interface trap charge의 생성과 산화막 내 positive fixed charge의 생성에 많은 영향을 끼침을 알 수 있었다. 그러므로 나노급 CMOSFET에 적용되는 strained-silicon MOSFET의 개발을 위해서는 소자의 성능 뿐 만 아니라 신뢰성 또한 고려되어야 한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.370-377
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• 2017

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.