• 한국공작기계학회:학술대회논문집
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• 한국공작기계학회 1996년도 춘계학술대회 논문집
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• pp.24-29
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• 1996

The seniconductor, which is precision product, requires many inspection processes. The surface conditions of the semiconductor chip effect on the functions of the semiconductors. The defects of the chip surface is crack or void. Because general inspection method requires many inspection processes, the inspection system which searches immediately and preciselythe defects of the semiconductor chip surface. We propose the inspection method by using the computer vision system. This study presents an image processing algorithm for inspecting the surface defects(crack, void)of the semiconductor test samples. The proposed image processing algorithm aims to reduce inspection time, and to analyze those experienced operator. This paper regards the chip surface as random texture, and deals with the image modeling of randon texture image for searching the surface defects. For texture modeling, we consider the relation of a pixel and neighborhood pixels as noncasul model and extract the statistical characteristics from the radom texture field by using the 2D AR model(Aut oregressive). This paper regards on image as the output of linear system, and considers the fidelity or intelligibility criteria for measuring the quality of an image or the performance of the processing techinque. This study utilizes the variance of prediction error which is computed by substituting the gary level of pixel of another texture field into the two dimensional AR(autoregressive model)model fitted to the texture field, estimate the parameter us-ing the PAA(parameter adaptation algorithm) and design the defect detection filter. Later, we next try to study the defect detection search algorithm.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.471-477
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• 2014

In this paper, a modeling and co-simulation methodology is proposed to predict the radiated electromagnetic interference (EMI) from on-chip switching I/O buffers. The output waveforms of I/O buffers are simulated including the on-chip I/O buffer circuit and the RC extracted on-chip interconnect netlist, package, and printed circuit board (PCB). In order to accurately estimate the EMI, a full-wave 3D simulation is performed including the measurement environment. The simulation results are compared with near-field electromagnetic scan results and far-field measurements from an anechoic chamber, and the sources of emission peaks were analyzed. For accurate far-field EMI simulation, PCB power trace models considering IC switching current paths and external power cable models must be considered for accurate EMI prediction. With the proposed EMI simulation model and flow, the electromagnetic compatibility can be tested even before the IC is fabricated.

• 대한금속재료학회지
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• 제46권5호
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• pp.310-314
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• 2008

Electromigration test of flip chip solder bump is performed at $140^{\circ}C$ C and $4.6{\times}10^4A/cm^2$ conditions in order to compare electromigration with thermomigration behaviors by using electroplated Sn-3.5Ag solder bump with Cu under-bump-metallurgy. As a result of measuring resistance with stressing time, failure mechanism of solder bump was evaluated to have four steps by the fail time. Discrete steps of resistance change during electromigration test are directly compared with microstructural evolution of cross-sectioned solder bump at each step. Thermal gradient in solder bump is very high and the contribution of thermomigration to atomic flux is comparable with pure electromigration effect.

• 한국광학회지
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• 제10권6호
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• pp.500-506
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• 1999

레이저 다이오드와 수신광검출기가 집적된 소자를 V-홈을 가진 실리콘 광학벤치에 flip-chip 본딩하고, 경사면을 가진 하나의 단일모드 광섬유와 수동정렬하는 방법을 사용하여 가입자망을 위한 저가의 양방향 송수신 모듈을 설계, 제작하였다. 광섬유의 단면 경사각에 따른 송신광결합 효율과 수신광결합 효율사이의 병목점을 찾기 위해 Gaussian빔 모델을 사용하여 수평정렬거리, 광섬유 단면 경사각, 수직정렬오차등의 변수에 따른 광결합계수를 계산함으로써, 최적의 광정렬조건을 예측하였다. 또한 실리콘 광학벤치에서 광결합효율을 측정하여 광섬유의 수직정렬오차에 따른 광결합계수의 감소가 광섬유의 경사각에 의해 보상될 수 있다는 계산결과의 타당함을 확인하였다. 실제의 sub-module 제작 및 광결합 실험에서 송신빔이 광섬유 단면에 반사되어 PD로 입사되는 것을 최소화하기 위하여 광섬유 단면을 경사절두원추형으로 제작함으로써 PD의 수신 잡음을 $30mu$m 이상의 정렬거리에서 -35dB이하로 유지할 수 있었다. 같은 조건에서 단면 경사각이 $12^{\circ}$인 광섬유에 의해 -12.1dB의 송신출력과 0.2A/W의 responsivity를 얻을 수 있었다.

• 전자통신동향분석
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• 제35권2호
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• pp.89-103
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
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• 제35권2호
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• pp.120-136
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 전자통신동향분석
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• 제35권2호
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• pp.104-119
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• 2020

Knowledge of the technology, characteristics, and market trends of the latest CPUs used in smartphones, computers, and supercomputers and the research trends of leading US university experts gives an edge to policy-makers, business executives, large investors, etc. To this end, we describe three topics in detail at a level that can help educate the non-majors to the extent possible. Topic 1 comprises the design and manufacture of a CPU and the technology and trends of the smartphone SoC. Topic 2 comprises the technology and trends of the x86 CPU and supercomputer, and Topic 3 involves an optical network chip that has the potential to emerge as a major semiconductor chip. We also describe three techniques and experiments that can be used to implement the optical network chip.

• 반도체디스플레이기술학회지
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• 제19권2호
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• pp.82-87
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• 2020

In this paper, we introduce the novel idea to improve the B/W usage efficiency of on-chip networks used for TAM to test multiple DRAMs. In order to avoid the local bottleneck of test packets caused by an ATE, we make test patterns using microcode-based instructions within ATE and adopt a test bus to transmit test responses from DRAM DFT (Design for Testability) called Test Generator (TG) to ATE. The proposed test platform will contribute to increasing the test economics of memory IC industry.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 추계학술대회 논문집
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• pp.602-605
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• 2000

Recently, a study of intellectual smell recognition system is applied for the various fields such as control of food processing and survey of decay. A basic gas recognition system was implemented gases using four metal oxides semiconductor sensors as inputs. A CPLD chip of twenty thousand gates level was used for this purpose. The CPLD chip was designed and the availability of the one chip smell recognition system was tested.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.422-424
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• 2009

본 논문은 반도체 제조 장비 중 몰드 장비에서 슬릿빔을 이용하여 칩 적층 높이를 측정하는 방법을 연구하였다. 본 논문에서는 슬릿빔을 이용한 높이 측정 방법의 기본 원리를 응용하여 반도체 제조 장비 안에 적용하면서 칩의 적층높이 측정 성능을 높이기 위하여 두 가지 방법을 연구하였다. 첫째로, 카메라 노출 시간과 높이 측정 반복성의 관계이며, 둘째는 PCB(Printed Circuit Board)휨 현상에 대한 측정 오류 최소화를 위하여 최소자승법을 응용하여 측정 성능을 향상 시킬 수 있었다.