• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.569-570
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• 2008

This paper proposed a new arbitration method in arbiter which is one of bus system components for the design of SoC. Considering compatibility between IP and bus system, the performance of bus system can change the performance of SoC chip. The proposed arbitration method achieved the performance improvement with high efficiency depending on the environment in use.

• Journal of Institute of Control, Robotics and Systems
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• v.10 no.4
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• pp.371-376
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• 2004

Distributed Network Protocol Version 3.0 (DNP3.0) is the communication protocol developed for the interoperability between a RTU and a central control station of SCADA in the power utility industry. In this paper DNP3.0 is implemented by using HDL with FPGA and C program on Hitachi H8/532 processor. DNP3.0 is implemented from physical layer to network layer in hardware level to reduce the computing load on a CPU. Finally, the ASIC for DNP3.0 has been manufactured from Hynix Semiconductor. The commercial feasibility of the hardware through the communication test with ASE2000 and DNP Master Simulator is performed. The developed protocol becomes one of IP, and can be used to implement SoC for the terminal device in SCADA systems. Also, the result can be applicable to various industrial controllers because it is implemented in HDL.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.175-180
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• 2003

In this paper, we present a new method for early depth test for a 3D rendering engine. We add a filter stage to the rasterizer in the 3D rendering engine, in an attempt to identify and avoid the occluded pixels. This filtering block determines if a pixel is hidden by a certain plane. If a pixel is hidden by the plane, it can be removed. The simulation results show that the filter reduces the number of pixels to the next stage up to 71.7%. As a result, 67% of memory bandwidth is saved with simple extra hardware.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.249-254
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• 2005

This paper presents a system-on-a-chip (SOC) design for digital TV. The single LSI incorporates almost all essential parts such as CPU, ISO/IEC 11172/13818 system/audio/video decoders, a video post-processor, a graphics/OSD processor and a display processor. It has analog IP's inside such as video DACs, an audio PLL, and a system PLL to reduce the system-level implementation cost. Descramblers and Smart Card interface are included to support widely used conditional access systems. The video decoder can decode two video streams simultaneously. The DSP-based audio decoder can process various audio coding specifications. The functional blocks for video quality enhancement also form outstanding features of this SoC. The SoC supports world-wide major DTV services including ATSC, ARIB, DVB, and DIRECTV.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.31-40
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• 2016

In vehicular ad-hoc networks (VANETs), vehicles sense information on emergency incidents (e.g., accidents, unexpected road conditions, etc.) and propagate this information to following vehicles and a server to share the information. However, this process of emergency message propagation is based on multiple broadcast messages and can lead to broadcast storms. To address this issue, in this work, we use a novel approach to detect the vehicles that are farthest away but within communication range of the transmitting vehicle. Specifically, we discuss a signal-to-noise ratio (SNR)-based linear back-off (SLB) scheme where vehicles implicitly detect their relative locations to the transmitter with respect to the SNR of the received packets. Once the relative locations are detected, nodes that are farther away will set a relatively shorter back-off to prioritize its forwarding process so that other vehicles can suppress their transmissions based on packet overhearing. We evaluate SLB using a realistic simulation environment which consists of a NS-3 VANET simulation environment, a software-based WiFi-IP gateway, and an ITS server operating on a separate machine. Comparisons with other broadcasting-based schemes indicate that SLB successfully propagates emergency messages with latencies and hop counts that is close to the experimental optimal while reducing the number of transmissions by as much as 1/20.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.42-50
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• 2006

Owing to the development of semiconductor processing technology, high density complex circuits can be integrated in a System-on-Chip (SoC). However, increasing energy consumption becomes one of the most important limiting factors. Power estimation at the early stage of design is essential, since design changes at lower levels may significantly lengthen the design period and increase the cost. In this paper, logic level circuits ire levelized and several levels are selected to build power model tables for efficient power estimation. The proposed techniques are applied to a set of ISCAS'85 benchmark circuits to illustrate their effectiveness. Experimental results show that significant improvement in estimation accuracy and slight improvement in efficiency are achieved when compared to those of a well-known existing method. The average estimation error has been reduced from $9.49\%\;to\;3.84\%$.

• Asia-Pacific Journal of Business Venturing and Entrepreneurship
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• v.9 no.2
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• pp.87-95
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• 2014

The High-price development & testing tools and IP infratstructures are required for the development of system semi-conductors, but SMEs have not ability to prepare for them. Recently in terms of the miniaturization and the advancement of semiconductor process, the cost of the semi-conductor development have shown the rising tendency and the market-based design tools used are requied to be upgraded due to the advancement in the environment and technology. On the contray, many other contries such as Taiwan, Japan, China, and User are supporting this system semi-conductor industry. Korean government is trying to build the research infrastructure for system semi-conductor industry that aims to reduce the costs of the design infrastructure investment, to support the companies of system semi-conductor development and to incubate the fab-less start-ups. This study analyzes the feasibility of the project, by using the AHP analysis and the results shows that this project is considered feasible because the AHP overall score is evaluated as 0.840, the overall score is greater than or equal to 0.55.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.6-11
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• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Journal of the Semiconductor & Display Technology
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• v.18 no.3
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• pp.122-126
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• 2019

These-days technology related to IoT (Internet of Thing) is widely used and there are many types of smart system based IoT like smart health, smart building and so on. In smart health system, it is possible to check someone's health by analyzing data from wearable IoT device like smart watch. Smart building system aims to collect data from sensor such as humidity, temperature, human counter like that and control the building for energy efficiency, security, safety and so forth. Furthermore, smart city system can comprise several smart systems like smart building, smart health, smart mobility, smart energy and etc. In this paper, we propose multimedia IoT based intelligent emergency alarm system for smart city. In existing IoT based smart system, it communicates lightweight data like text data. In the past, due to network's limitations lightweight IoT protocol was proposed for communicating data between things but now network technology develops, problem which is to communicate heavy data is solving. The proposed system obtains video from IP cameras/CCTVs, analyses the video by exploiting AI algorithm for detecting emergencies and prevents them which cause damage or death. If emergency is detected, the proposed system sends warning message that emergency may occur to people or agencies. We built prototype of the intelligent emergency alarm system based on MQTT and assured that the system detected dangerous situation and sent alarm messages. From the test results, it is expected that the system can prevent damages of people, nature and save human life from emergency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.286-292
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• 2012

Scan techniques are almost mandatorily adopted in designing current System-on-a-Chip (SoC) to enhance testability, but inadvertently secret keys can be stolen through the scan test channels of crypto SoCs. An efficient scan design technique is proposed in this paper to protect the secret key of an Advanced Encryption Standard (AES) core embedded in an SoC. A new instruction is added to IEEE 1149.1 boundary scan to use a fake key instead of user key, in which the fake key is chosen with meticulous care to improve the testability as well. Our approach can be implemented as user defined logic with conventional boundary scan design, hence no modification is necessary to any crypto IP core. Conformance to the IEEE 1149.1 standards is completely preserved while yielding better performance of area, power, and fault coverage with highly robust protection of the secret user key.