• 대한전기학회논문지
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• 제41권2호
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• pp.170-177
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• 1992

Contact resistance and contact leakage current of the Al/TiSiS12T/Si system are investigated for NS0+T and PS0+T junctions. SALICIDE (Self Aligned Silicide) process was used to make the Al/TiSiS12T/Si system. Titanium disilicide is one of the most common silicides because of its thermal stability, ability to form selective formation and low resistivity. In this paper, RTA temperature effect and Junction implant dose effect were evaluated to characterize contact resistance and contact leakage current. The TiSiS12T contact resistance to NS0+T silicon is lower than that to PS0+T silicon, and TiSiS12T of contact leakage current to NS0+T silicon is lower than that to PS0+T silicon. Contact resistance and contact leakage current of the Al/TiSiS12T/Si system by this method were possible for VLSI application.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1564-1567
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• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1997년도 한국재료학회 춘계학술발표회
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• pp.27-27
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• 1997

• JSTS:Journal of Semiconductor Technology and Science
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• 제1권1호
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1997년도 한국재료학회 추계학술발표회
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• pp.128-128
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• 1997

• 대한전자공학회논문지
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• 제23권6호
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• pp.741-746
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• 1986

A novel n-p-n bipolar transistor of which emitter is self-aligned with base contact by polyilicon is developed for using in high speed and high packing density LSI circuits. The emitter of this transistor is separated less than 0.4 \ulcorner with base contact by self-aligh technology, and the emitter feature size is less than 3x5 \ulcorner\ulcorner Because the active region of this transistor is not damaged through all the process, it has excellent electric properties. Using the n-p-n transistors by 3.0\ulcorner design rules, a NTL ring oscillator has 380 ps, a CML ring oscillator has 390ps, and a I\ulcorner ring oscillator has 5.6ns of per-gate minimum propagation delay time.

• 전자공학회논문지A
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• 제32A권5호
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• pp.54-59
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• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• 대한전기학회논문지
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• 제45권2호
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• pp.249-255
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• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• 한국진공학회지
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• 제15권4호
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• pp.354-359
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• 2006

일반적인 포토리소그래피를 사용하지 않고 마이크로미터 혹은 나노미터 단위의 패턴형성을 위한 연구가 최근 많은 연구그룹에 의해 진행되고 있다. 본 실험에서는 패턴이 형성된 polydimelthylsiloxane (PDMS) 몰드를 octadecyltrichlorosilane (OTS) 용액에 dipping 하여 PDMS 표변에 OTS 단분자막을 형성하고 micro contact printing (${\mu}-CP$) 방법으로 OTS 단분자 막을 유리기판 표면위로 전사하였다. 전사된 OTS 단분자막은 친수성 유리기판 위에서 소수성 표면특성을 갖게 하며, 친수성은 용액 속에 dipping 하였을 때 소수성 표면 위에는 코팅되지 않도록 한 이 방법을 이용하여 유리기판 위에 Ag 패턴을 형성하였다. 또한, 세척직후 친수성 표면 특성을 보이는 유리기판의 시간에 따른 접촉각 측정을 통해 표면에너지의 변화를 분석하였다.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2001년도 High Temperature Superconductivity Vol.XI
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• pp.33-33
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• 2001