• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.258-258
• /
• 2012

플렉시블 디스플레이를 위해 저온 공정은 필수적이며, 이를 위해 플라스틱 기판을 이용한 연구가 한창 진행 중이다. 이번 연구에서는 도핑처리 하지않고 알루미늄을 이용한 self-aligned 소오스-드레인 구조의 비휘발성 메모리를 ELA 폴리실리콘 기판 상에 제작하였다. 소오스-드레인 부분은 lift-off 공정을 이용하여 pattern 작업을 진행하였다. $250^{\circ}C$에서 1시간의 후속 열처리 공정을 진행한 self-aligned 소오스-드레인 구조의 비휘발성 메모리는 후속 열처리 공정을 진행하지 않았을 때와 비교하여 다음과 같은 메모리의 특성향상을 나타내었다. 메모리 윈도우 특성의 경우 1.15 V에서 3.47 V의 커다란 증가를 보였으며 retention 특성의 경우 12%에서 46%로 증가하였다. 이를 통해 비록 도핑 되지 않은 비휘발성 메모리 소자일지라도 self-aligned 구조와 저온 열처리를 이용할 시 향후 플렉시블 전자소자에의 적용이 가능함을 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.59 no.4
• /
• pp.450-455
• /
• 2010

The performance modeling of a $25{\mu}m$ pitch VGA ${\mu}$-bolometer with the self-aligned thermal resistor structure is carried out. The self-aligned thermal resistor can be utilized for the maximizing the thermal resistance and the fill factor of a bolometer, so the performance improvement can be expected. From the results of the performance modeling of the micro-bolometer with self-align thermal resistor for a $25{\mu}m$ pitch $640{\times}480$ microbolometer designed with $0.6{\mu}m$ minimum feature size, the drastic improvements of NETD from 38.7 mK to 19.1 mK, responsivity of 1.9 times are expected with a self aligned thermal resistor structure. The main reason for the performance improvements with a self-aligned thermal resistor structure comes from the increasement of the thermal resistance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.19 no.4
• /
• pp.367-372
• /
• 2006

A carbon nanotube field emission display(CNT FED) panel with a 2 inch diagonal size was fabricated using a screen printing of a prepared photo-sensitive CNT paste and vacuum in-line sealing technology. After a surface treatment of the patterned CNT, only the carbon nanotube tips are uniformly exposed on the surface. The diameter of the exposed CNTs are usually about 20 nm. Using the photo-sensitive CNT paste, we have developed a triode type CNT FEA with a self-aligned gate-emitter structure. The turn on voltage was around 100 V which corresponds to according the turn on field of about $40V/{\mu}m$. By the creation of a self-aligned gate-emitter structure, it is expected that the screen printed photo-sensitive CNT paste is promising as a good candidate for the large size field emission display.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.36 no.7
• /
• pp.462-469
• /
• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.5
• /
• pp.54-59
• /
• 1995

We have proposed a novel self-aligned offset gated polysilicon TFTs device without an offset mask in order to reduce a leakage current and suppress a kink effect. The photolithographic process steps of the new TFTs device are identical to those of conventional non-offset structure TFTs and an additional mask to fabricate an offset structure is not required in our device due to the self-aligned process. The new device has demonstrated a lower leakage current and a better ON/OFF current ratio compared with the conventional non-offset device. The new TFT device also exhibits a considerable reduction of the kink effect because a very thin film TFT devices may be easily fabricated due to the elimination of contact over-etch problem.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 1997.10a
• /
• pp.128-128
• /
• 1997

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.32 no.6
• /
• pp.448-453
• /
• 2019

This work reports the electrical characteristics of and temperature distribution in chalcogenide phase change memory (PCM) devices that have a self-aligned structure. GST (Ge-Sb-Te) chalcogenide alloy films were formed in a self-aligned manner by interdiffusion between sputter-deposited Ge and $Sb_2Te_3$ films during thermal annealing. A transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis demonstrated that the local composition of the GST alloy differed significantly and that a $Ge_2Sb_2Te_5$ intermediate layer was formed near the $Ge/Sb_2Te_3$ interface. The programming current and threshold switching voltage of the PCM device were much smaller than those of a control device; this implies that a phase transition occurred only in the $Ge_2Sb_2Te_5$ intermediate layer and not in the entire thickness of the GST alloy. It was confirmed by computer simulation, that the localized phase transition and heat loss suppression of the GST alloy promoted a temperature rise in the PCM device.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2009.11a
• /
• pp.13.2-13.2
• /
• 2009

전도성 고분자는 재료의 경제적 측면 이외에 반도체로서의 다양한 전기적 특성, 생물학적 적합성, 다양한 합성 가능성 등의 우수한 장점을 지니고있어 많은 분야에 응용되고 있다. 그러나 유기물질이라는 한계로 인하여 기존 nano/microfabrication에서 일반적으로 적용되는 패터닝 방법을 적용하는데 어려움이있다. 따라서 많은 연구자들이 독립적인 나노 크기 개체를 만든 후 이의 자가 조립, 혹은 이와 유사한 방법에 의해 소자를 형성하고자 하는 노력을 기울이고 있다.이러한 bottom-up방식에 의한 소자 구성은 나노크기의 전도성 고분자 물질을 소자화하는데에는 성공하고 있으나, 복잡한 패터닝과 다양한 크기의 나노구조체를 정확한 위치에 정렬시키는 문제에 있어서 명확한 해답을 제시하지 못하는 실정이다. 본 연구에서는 현재 보편적으로 이용되고 있는 금속의nano/microfabrication공정과 전도성 폴리머의 전해합성를 복합화하여 고정밀도 및 다양한 패턴의 나노 소자를 구현하고자하였다. 이를 위하여 전해합성 조건에 따른 polypyrrole의전기적 특성을 평가하였으며, 하부 금속전극관의 복합적층화를 통한 접촉저항의 최소화를 구현하고자 하였다. 또한 이와 같은 self-alignedelectropolymerization방법을 이용하여 구성된 nano/micro 소자의 gas sensor 및 bio sensor로서의 적용가능성에 대하여평가하였다.

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.45 no.2
• /
• pp.249-255
• /
• 1996

A self-aligned latch-up suppressed IGBT has been proposed and the process method and the device characteristics of the IGBT have been verified by numerical simulation. As the source is laterally diffused through the sidewall of the trench in the middle of the body, the size of the source is small and the doping concentration of the source is lower than that of the p++ body and the emitter efficiency of the parasitic npn transistor is low so that latch-up may be suppressed. No additional mask steps for p++ region, source, and source contact are required so that small sized body can be obtained Latch-u current density higher than 10000 A/cm$^{2}$ have been achieved by adjusting the process conditions.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.21-28
• /
• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.