• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제11권4호
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• pp.261-266
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• 1998

In developing the high density memory device, the etching of fine pattern is becoming increasingly important. Therefore, definition of ultra fine line and space pattern and minimization of damage and contamination are essential process. Also, the high density plasma in low operating pressure is necessary. The candidates of high density plasma sources are electron cyclotron resonance plasma, helicon wave plasma, helical resonator, and inductively coupled plasma. In this study, planar type magnetized inductively coupled plasma etcher has been built. The density and temperature of Ar plasma are measured as a function of rf power, flow rate, external magnetic field, and pressure. The oxide etch rate and selectivity to polysilicon are measured as the above mentioned conditions and self-bias voltage.

• Proceedings of the Korean Nuclear Society Conference
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• 한국원자력학회 1997년도 춘계학술발표회논문집(2)
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• pp.223-230
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• 1997

최근들어 그 활용도가 점점 증대되고 있는 DLU(Diamond-like Carbon) /Diamond 박막(thin film)의 합성기술을 개발하여 원자력분야에 응용하고자 시도하였다. 이를 위하여 13.56 MHz의 고주파(RF: radio-frequency)를 사용하는 플라즈마 화학증착(PECVD: Plasma Enhanced Chemical Vapor Deposition) 장치를 직접 제작하여 탄소함유(CH$_4$, $CO_2$...등) 기체로부터 기본적인 DLC 박막증착시험을 수행하였다. 실험은 진공증착기(vacuum chamber)내의 압력(pressure), 탄소함유 기체의 조성비, 그리고 바이어스전압(negative self-bias voltage)둥을 변화시키면서 수행하였다. 증착속도(deposition rate)는 증착층의 두께를 알파스템($\alpha$-step)으로 측정하여 결정하였으며, 이로부터 증착속도가 압력 및 바이어스 전압의 증가에 따라 증가함을 알 수 있었다. 또한 바이어스 전압 300V 이상에서 $CO_2$량 증가가 증착속도를 촉진시킨다는 사실도 확인하였다. 그리고 EPMA(electron probe micro-analyser) 및 Raman 스펙트럼분석을 통하여 증착층의 구조가 DLC 임을 확인하였다.

• Proceedings of the KIEE Conference
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국해양정보통신학회 2005년도 추계종합학술대회
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• pp.869-872
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• 2005

This paper presents a new switchable dual mode VCO(Voltage-Controlled Oscillator). The VCO is efficient in dual mode operation and has self-bias adjustment based on the operation frequencies of 2.4 GHz and 5 GHz. The switching is done using MOS transistors and tuning is done using MOS varactors. It is implemented using TSMC 0.18${\mu}$m CMOS technology. It is powered by 1.8V supply. The measured results showed that the overall tuning range is approximately 13% at 5 GHz and 8% at 2.4 GHz. The measured phase noise is approximately -102 dBc/Hz at 1 MHz offset for 5 GHz and -89 dBc/Hz at 600kHz offset for 2.4 GHz. The VCO showed tail currents of 2mA in 5GHz mode and 2.5mA in 2.4GHz mode from a 1.8 V supply, respectively.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• 제19권4호
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• pp.1-8
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• 2005

Plasma researches using parallel-plate electrodes are widely used in semiconductor application such as etching and thin film deposition. Therefore, a quantitative understanding and control of plasma behavior are becoming increasingly necessary because their important applications and simulation techniques have been actively carried out in order to solve such problems above. In this paper, we developed a two-dimensional(2D) self-consistent fluid model, because 2D models can deal with real reactor geometries. The fluid model is based on particle continuity equations for taking account of an electrode system in a cylindrical geometry. An pure Ar gas was used at 500[mTorr] and radio-frequency (13.56(MHz)). Four models were simulated under the different electrode geometries which have chamber widths of 5.25, 6.0, 8.0, and 10.0[cm] and we compared their results with each other. Plasma uniformity and a do self-bias voltage were also discussed.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• 제10권1호
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• pp.42-48
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• 2011

In this paper, a passive load-pull using a GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip in X-band is presented. To obtain operation conditions that characteristic change by self-heating was minimized, pulsed drain bias voltage and pulsed-RF signal is employed. An accuracy impedance matching circuits considered parasitic components such as wire-bonding effect at the boundary of the drain is accomplished through the use of a electro-magnetic simulation and a circuit simulation. The microstrip line length-tunable matching circuit is employed to adjust the impedance. The measured maximum output power and drain efficiency of the pulsed load-pull are 42.46 dBm and 58.7%, respectively, across the 8.5-9.2 GHz band.

• Journal of the Institute of Electronics Engineers of Korea SC
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• 제37권2호
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• pp.60-68
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• 2000

This paper describes a design methodology for the CMOS current source which can be implemented in standard memory process. The proposed techniques provide a good characteristic against the power-supply variation by utilizing a self-bias circuit and the reduction of the first-order component of the temperature variation through the new temperature compensation technique and include a new current-sensing start-up circuit enabling a robust operation against the voltage noise generated during the operation of the chip. In addition to the circuit-design technology, techniques where the proposed CMOS current-reference circuit can be applied to the clocking circuits of a very high-speed DRAM are presented. The feasibility of the suggested design methodology for the CMOS current reference is demonstrated by both the analytical method and the circuit simulation.

• ETRI Journal
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• 제39권2호
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• pp.292-299
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• 2017

We propose pulse-mode dynamic $R_on$ measurement as a method for analyzing the effect of stress on large-scale high-power AlGaN/GaN HFETs. The measurements were carried out under the soft-switching condition (zero-voltage switching) and aimed to minimize the self-heating problem that exists with the conventional hard-switching measurement. The dynamic $R_on$ of the fabricated AlGaN/GaN MIS-HFETs was measured under different stabilization time conditions. To do so, the drain-gate bias is set to zero after applying the off-state stress. As the stabilization time increased from $ 0.1{\mu}s$ to 100 ms, the dynamic $R_on$ decreased from $160\Omega$ to $2\Omega$. This method will be useful in developing high-performance GaN power FETs suitable for use in high-efficiency converter/inverter topology design.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.124-124
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• 2010

Currently, extreme ultraviolet lithography (EUVL) is being investigated for next generation lithography. EUVL is one of competitive lithographic technologies for sub-22nm fabrication of nano-scale Si devices that can possibly replace the conventional photolithography used to make today's microcircuits. Among the core EUVL technologies, mask fabrication is of considerable importance due to the use of new reflective optics having a completely different configuration compared to those of conventional photolithography. Therefore, new materials and new mask fabrication process are required for high performance EUVL mask fabrication. This study investigated the etching properties of SnO2 (Tin Oxide) as a new absorber material for EUVL binary mask. The EUVL mask structure used for etching is SnO2 (absorber layer) / Ru (capping / etch stop layer) / Mo-Si multilayer (reflective layer) / Si (substrate). Since the Ru etch stop layer should not be etched, infinitely high selectivity of SnO2 layer to Ru ESL is required. To obtain infinitely high etch selectivity and very low LER (line edge roughness) values, etch parameters of gas flow ratio, top electrode power, dc self - bias voltage (Vdc), and etch time were varied in inductively coupled Cl2/Ar plasmas. For certain process window, infinitely high etch selectivity of SnO2 to Ru ESL could be obtained by optimizing the process parameters. Etch characteristics were measured by on scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) analyses. Detailed mechanisms for ultra-high etch selectivity will be discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권2호
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• pp.83-87
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• 2004

Phase noise performance and current consumption of Radio Frequency (RF) Voltage-Controlled Oscillator (VCO) are largely dependent on the Quality (Q) factor of inductor-capacitor (LC) tank. Because the Q-factor of LC tank is determined by on-chip spiral inductor, we designed, analyzed, and modeled on-chip differential inductor to enhance differential Q-factor, reduce current consumption and save silicon area. The simulated inductance is 3.3 nH and Q-factor is 15 at 2 GHz. Self-resonance frequency is as high as 13 GHz. To verify its use to RF applications, we designed 2 GHz differential LC VCO. The measurement result of phase noise is -112 dBc/Hz at an offset frequency of 100 kHz from a 2GHz carrier frequency. Tuning range is about 500 MHz (25%), and current consumption varies from 5mA to 8.4 mA using bias control technique. Implemented in $0.35-{\mu}m$ SiGe BiCMOS technology, the VCO occupies $400\;um{\times}800\;um$ of silicon area.