• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.4
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• pp.91-103
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• 2009

A cryptographic module (CM) is an implementation of various cryptographic algorithms and functions by means of hardware or software, When a CM is validated or certified under the CM validation program(CMVP), a finite state model(FSM) of the CM should be developed and provided, However, guides or methods of modeling and analysis of a FSM is not well-known, because the guide is occasionally regarded as a proprietary know-how by developers as well as verifiers of the CM. In this paper, we propose a set of guides on modeling and analysis of a FSM, which is needed for validation of a CM under CMVP, and a transition test path generation algorithm, as well as implement a simple modeling tool (CM-Statecharter). A FSM of a CM is modeled by using the Statechart of UML 2.0, Statechart, overcoming weakness of a FSM, is a formal and easy specification model for finite state modeling of a CM.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.601-606
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• 2005

Recently with the high expectation of voice over WLAN service, to supped fast inter-AP security transition in WLAN AP is one of the most actively investigating issues. It is also very important to minimize inter-AP security transition latency, while maintaining constantly the secure association from old AP when a station transits to new AP. Hence, this paper first defines secure transition latency as a primary performance metric of AP system in WLAN supporting IEEE802.11i, 802.1x, and 802.11f, and then presents low latency inter-AP security transition mechanism and its security FSM whose objective is to minimize inter-AP transition latency. Experiment shows that the proposed scheme outperforms the legacy 802.1X AP up to $79\%$ with regard to the transition latency.

• Journal of Navigation and Port Research
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• v.29 no.6 s.102
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• pp.487-493
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• 2005

Since the destruction of World Trade Center the attention of the United States and the wider international community has focussed upon the need to strengthen security and prevent terrorism This paper suggests an analysis prior to risk factor and structure for anti-terrorism in the korean maritime society. For this, in this paper, maritime terror risk factor was extracted by type and case of terror using brainstorming method. Also, risk factor is structured by FSM method and analyzed for ranking of each risk factor by AHP. At the result, the evaluation of risk factor is especially over maximum factor for related external impact.

• Smart Media Journal
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• v.4 no.4
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• pp.39-46
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• 2015

This paper describes hardware implementation of the encryption block of the '128 bit block cipher LEA' among various lightweight encryption algorithms for IoT (Internet of Things) security. Round function blocks and key-schedule blocks are designed by parallel circuits for high throughput. The encryption blocks support secret-key of 128 bits, and are designed by FSM method and 24/n stage(n=1, 2, 3, 4, 8, 12) pipeline methods. The LEA-128 encryption blocks are modeled using Verilog-HDL and implemented on FPGA, and according to the synthesis results, minimum area and maximum throughput are provided.

• Convergence Security Journal
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• v.13 no.4
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• pp.19-25
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• 2013

The increasing demand for fast, flexible and guaranteed Quality of Service (QoS) in core networks has caused to deploy MultiProtocol Label Switching (MPLS) and Generalized MPLS (GMPLS) control plane. In GMPLS control plane, path computation and cooperation processes are one of the crucial element to maintain an acceptable level of service. The Internet Engineering Task Force (IETF) has proposed the Path Computation Element (PCE) architecture. The PCE is a dedicated network element devoted to path computation process and communications between Path Computation Clients (PCC) and PCEs is realized through the PCE Protocol (PCEP). This paper examines the PCE-based path computation architecture to include the design and implementation of PCEP. The functional modules including Finite State Machine (FSM) and related key design issues of each state are presented. In particular we also discuss internal/external protocol interfaces that efficiently control the communication channels.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2004.11a
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• pp.343-348
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• 2004

Since the destruction of World Trade Center the attention of the united States and the wider international community has focussed upon the need to strengthen security and prevent terrorism. This paper suggests an analysis prior to risk factor and structure for anti-terrorism in the korean maritime society. For this, in this paper, maritime terror risk factor was extracted by type and case of terror using brainstorming method. Also, risk factor is structured by FSM method and analyzed for ranking of each risk factor by AHP. At the result, the evaluation of risk factor is especially over maximum factor for related external impact.

• International Journal of Computer Science & Network Security
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• v.21 no.7
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• pp.233-240
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• 2021

The majority of the Web's success can be related to its productivity and flexibility. Web Services (WSs) have the means to create new patterns for the delivery of software capabilities. The WS easily provides the use of existing components available via the Internet. WSs are a new trend that shares ubiquitous systems with others, so the popularity of the Web is increased day by day with their associated systems. This paper will explore and adopt the possibility of developing a technique that will automate instructors' scheduling of timetables within a Web services environment. This technique has an advantage that facilitates users to reduce the time cost and effort by reducing errors and costs for institutes. Providing dependable tables to avoid mistakes related to instituting schedules is ensured by an automated repetitive manual procedure. Automated systems are increasingly developed based on organizations and their customers. Still, the setting's difficulty of automation systems increases to rise as the system architecture and applications must accomplish various requirements and specifications of ever-demanding project scenarios. The automation system is composed of an operating system, platforms, devices, machines, control system, and information technology. This architecture provides more productivity and optimized services. The main purpose of this paper is to apply an automation system to enhance both quality and productivity. This paper also covers an agile method of proving an automation system by Finite State Machine (FSM) and Attributed Graph Grammar (AGG) tool.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.1233-1236
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• 2004

보안 시스템에서 접근 통제 모델을 사용하는 가장 중요한 목적은 시스템 및 사용자에 대한 안정성을 보장하기 위해서이다. 본 논문에서 다루고 있는, SPR은 보안 시스템의 행위를 유한 상태 기계(FSM) 기반의 보안모델로 표현한 후, 보안 모델에 대한 초기 상태의 안전성을 검사하고 초기 상태에서 다음 상태로 전이가 존재할 경우에 그 상태들에 대응하는 모든 상태들에 대해서 보안기준을 만족하는지 검증하는 도구이다. 본 논문에서는 SPR를 사용하여 현재 많은 사람들이 이용하는 Windows 운영 체제의 NTFS에 기반을 둔 보안모델의 안전성을 검증하는 방법을 소개한다

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• The Journal of the Korea Contents Association
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• v.9 no.11
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• pp.74-79
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• 2009

This paper proposes a hardware structure and associated finite state machine designs sharing key scheduling circuitry to enhance the performance of the block cypher algorithm, HIGHT. It also introduces an efficient protocol applicable to RFID systems comprising the HIGHT block cipher algorithm. The new HIGHT structure occupies an area size small enough to accommodate tag applications. The structure yields twice higher performance them conventional HIGHT algorithms. The proposed protocol overcomes the security vulnerability of RFID tags and thereby strengthens the security of personal information.