• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.69-78
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• 1999

In this paper, direct conversion receiver was designed to even harmonic anti-paralled diode pair ring mixer. Using a second harmonic component of LO instead of LO signal and RF signal are mixed by SHP(Sub Harmonic Pumped) mixer with anti-parallel diode pair. Canceling the harmonics of LO signal in ring mixer, SHP mixer using anti-parallel diode pair could mostly reduce the radiation of LO signal through a input port the most, good isolation characteristic, and low spurious characteristic by LO signal was shown over broad band. The produced SHP mixer showed LO/IF, RF/IF and LO/RF isolation was 24.6dB,36.2dB and 22.5dB respectively. And conversion loss was measured 15.6dB, IF output -35.6dBm with -20dBm RF input and 5.5dBm LO signal. 1dB compression point of If signal, in respect to RF signal, was found at the 0dbm RF signal.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.5
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• pp.468-474
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• 2010

In this paper, a VCHO(Voltage Controlled Harmonic Oscillator) for K-band application has been designed and implemented. The proposed oscillator has a structure of two hair-pin resonators placed on input and output of active device. Using in/out common frequency tuning structure, the VCHO yields some advantages of the enhanced fundamental frequency suppression characteristic as well as the improved output power of second harmonic. According to implementation and measurement results, it was shown that a VCHO provides an output power of -2.41 dBm, a fundamental frequency suppression of -21.84 dBc, and phase noise of -101.44 dBc/Hz at 100 kHz offset. In addition, as for the bias voltage from 0 V to -10 V for the varactor diode, output frequency range of 10.58 MHz is obtained with a power variation of ${\pm}0.19\;dB$ over its frequency range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.783-789
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• 2015

This paper presents a Doherty power amplifier(DPA) operating in the 2.6 GHz band for long term evolution(LTE) systems. In order to achieve high efficiency, second and third harmonic impedances are controlled using a compact output matching network. The DPA was implemented using a gallium nitride high electron mobility transistor(GaN-HEMT) that has many advantages, such as high power density and high efficiency. The implemented DPA was measured using an LTE downlink signal with a 10 MHz bandwidth and 6.5 dB PAPR. The implemented DPA exhibited a gain of 13.1 dB, a power-added efficiency(PAE) of 57.6 %, and an ACLR of -25.7 dBc at an average output power of 33.4 dBm.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.46 no.3
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• pp.237-243
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• 2018

In this study, the hub vibration load characteristic is evaluated for a rotor in high advance ratio conditions while investigating blade loads through the structural load prediction and harmonic analysis. Numerical studies are performed to validate the wind tunnel test data performed in NASA as the rotor advance ratios are varied from 0.40 to 0.71. A good correlation is obtained for rotor performance calculation at the range of advance ratios considered. It is observed that the hub vibration loads remain almost unchanged when the advance ratios are higher than 0.5, even though the amplitudes of blade structural loads become larger with increasing advance ratios. A harmonic analysis on blade moments is confirmed that the dominant structural mode is 3/rev component for flap bending moments and 4/rev for lag bending moments. The reason is due to the tendency of the second flap and lag mode frequencies which approach 3/rev and 4/rev, respectively, as the advance ratios are increased.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.32-37
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• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• Smart Structures and Systems
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• v.9 no.2
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• pp.165-188
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• 2012

In the first part of the paper, the optimal design parameters for tuned liquid column dampers (TLCD) in harmonic pitching motion were investigated. The configurations in design tables include uniform and non-uniform TLCDs with cross-sectional ratios of 0.3, 0.6, 1, 2 and 3 for the design in different situations. A closed-form solution of the structural response was used for performing numerical optimization. The results from optimization indicate that the optimal structural response always occurs when the two resonant peaks along the frequency axis are equal. The optimal frequency tuning ratio, optimal head loss coefficient, the corresponding response and other useful quantities are constructed in design tables as a guideline for practitioners. As the value of the head loss coefficient is only available through experiments, in the second part of the paper, the prediction of head loss coefficients in the form of a design chart are proposed based on a series of large scale tests in pitching base motions, aiming to ease the predicament of lacking the information of head loss for those who wishes to make designs without going through experimentation. A large extent of TLCDs with cross-sectional ratios of 0.3, 0.6, 1, 2 and 3 and orifice blocking ratios ranging from 0%, 20%, 40%, 60% to 80% were inspected by means of a closed-form solution under harmonic base motion for identification. For the convenience of practical use, the corresponding empirical formulas for predicting head loss coefficients of TLCDs in relation to the cross-sectional ratio and the orifice blocking ratio were also proposed. For supplemental information to horizontal base motion, the relation of head loss values versus blocking ratios and the corresponding empirical formulas were also presented in the end.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.122-128
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• 2005

In this paper, a low noise parallel feedback oscillator for harmonic suppression and a frequency doubler are designed and implemented. As the fundamental signal of the oscillator for frequency doubling is extracted between the dielectric resonator (DR) filter and the gate device of the active device, the undesired harmonics at the output of the oscillator is remarkably suppressed. The fundamental signal of the oscillator for frequency doubling directly feeds to the frequency doubler without an additional band pass filter for harmonic suppression. The second harmonic suppression of -47.7 dBc at the oscillator output is achieved, while the fundamental suppression of -37.5 dBc at the doubler output is obtained. The phase noise characteristics are -80.3 dBc/Hz and -93.5 dBc/Hz at the offset frequency of 10 KHz and 100 KHz from the carrier, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.

• Journal of IKEEE
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• v.26 no.1
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• pp.95-103
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• 2022

In this paper, the efficiency of a sensorless method with square-wave injection for a low-cost inverter, so called B4 inverter is presented. This inverter comprises only 4 switches to reduce system cost. It is distinguished from the conventional B6 inverter that has 6 of switching elements. The B4 inverter, injected a 1 kHz of harmonic wave, has been modelled using the functions and library in Matlab/Simulink. This paper described each component of sensorless algorithm. Among them, the Notch Filter is used to extract the harmonic component of the phase current and a second-order low-pass filter was used to reduce the ripple of the estimated speed. It is shown through simulation that the rotor angle of a permanent magnet synchronous motor is detected by multiplying the current waveform extracted using the notch filter by the harmonic voltage. The feasibility of the proposed method is shown through Simulink simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.60-68
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• 2007

A technique is presented to extract differential second harmonic output from common source nodes of a cross-coupled P-& N-FET oscillator. Provided the impedances at the common source nodes are optimized and the fundamental swing at the VCO core stays in a proper mode, it is found that the amplitude and phase errors can be kept within $0{\sim}1.6dB$ and $+2.2^{\circ}{\sim}-5.6^{\circ}$, respectively, over all process/temperature/voltage corners. Moreover, an impedance-tuning circuit is proposed to compensate any unexpectedly high errors on the differential signal output. A Prototype 5-GHz VCO with a 2.5-Hz LC resonator is implemented in $0.18-{\mu}m$ CMOS. The error signal between the differential outputs has been measured to be as low as -70 dBm with the aid of the tuning circuit. It implies the push-push outputs are satisfactorily differential with the amplitude and phase errors well less than 0.34 dB and $1^{\circ}$, respectively.