• Journal of the Korea Society of Computer and Information
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• 제17권11호
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• pp.1-10
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• 2012

In this paper, the extension of the addressing mode in the 16-bit Thumb instruction set architecture is proposed to improve the performance of 16-bit Thumb code. The key idea of the proposed approach is the introduction of new addressing modes for more frequent instructions by using the saved bits from the reduction of the register fields in less frequently used instructions. The proposed approach adopts efficient addressing modes from the 32-bit ARM architecture, which is the superset of the 16-bit Thumb architecture. To speed up access to a data list, scaled register offset addressing mode and post-indexed addressing mode are introduced for load and store instructions. Experiments show that the proposed approach improves performance by an average of 8.5% when compared to the conventional approach.

• Agribusiness and Information Management
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• 제1권2호
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• pp.43-60
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• 2009

To improve the performance of wide-issue superscalar processors, it is essential to increase the width of instruction fetch and the issue rate. Removal of control hazard has been put forward as a significant new source of instruction-level parallelism for superscalar processors and the conditional branch prediction is an important technique for improving processor performance. Branch mispredictions, however, waste a large number of cycles, inhibit out-of-order execution, and waste electric power on mis-speculated instructions. Hence, the branch predictor with higher accuracy is necessary for good processor performance. In global-history-based predictors like gshare and GAg, many mispredictions come from commit update of the branch history. Some works on this subject have discussed the need for speculative update of the history and recovery mechanisms for branch mispredictions. In this paper, we present a new mechanism for recovering the branch history after a misprediction. The proposed mechanism adds an age_counter to the original predictor and doubles the size of the branch history register. The age_counter counts the number of outstanding branches and uses it to recover the branch history register. Simulation results on the SimpleScalar 3.0/PISA tool set and the SPECINT95 benchmarks show that gshare and GAg with the proposed recovery mechanism improved the average prediction accuracy by 2.14% and 9.21%, respectively and the average IPC by 8.75% and 18.08%, respectively over the original predictor.

• Journal of Sensor Science and Technology
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• 제27권1호
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• pp.31-35
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• 2018

This paper describes a low-power, SNDR (signal-to-noise and distortion ration) enhanced SAR (successive approximation register) type 12b ADC (analog-to-digital converter) with noise shaping technique. For low power consumption and small chip size of the DAC (digital-to-analog converter), the top plate sampling technique and the dummy capacitor switching technique are used to implement 12b operation with a 10b capacitor array in DAC. Noise shaping technique is applied to improve the SNDR by reducing the errors from the mismatching of DAC capacitor arrays, the errors caused by attenuation capacitor and the errors from the comparator noise. The proposed SAR ADC is designed with a $0.18{\mu}m$ CMOS process. The simulation results show that the SNDR of the SAR ADC without the noise shaping technique is 71 dB and that of the SAR ADC with the noise shaping technique is 84 dB. We can achieve the 13 dB improvement in SNDR with this noise shaping technique. The power consumption is $73.8{\mu}W$ and the FoM (figure-of-merit) is 5.2fJ/conversion-step.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2003년도 가을 학술발표논문집 Vol.30 No.2 (1)
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• pp.196-198
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• 2003

Virtually every digital signal processors(DSPs) support on-chip multi- memory banks that allow the processor to access multiple words of data from memory in a single instruction cycle. Also, all existing fixed-point DSPs have irregular architecture of heterogeneous register which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multi-memory banks, most of them assumed processors with relatively simple, homogeneous general-purpose resisters. Therefore, several vendor-provided compilers fer DSPs were unable to efficiently assign data to multiple data memory banks. thereby often failing to generate highly optimized code fer their machines. This paper presents an algorithm that helps the compiler to efficiently assign data to multi- memory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly-coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable In quality to the code generated by a coupled approach

• Journal of the Korea Society of Computer and Information
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• 제24권8호
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• pp.105-111
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• 2019

In this paper, I introduce the development of a system to register Korean standard technical terms which are corresponded with English electronical terminologies on the Electropedia of the International Electronical Committee(IEC). In 2016, this project was started with the permission of registration at the Technical Committee 1 of the $80^{th}$ IEC General Meeting in Frankfurt, Germany. The work was consisted of 3 parts, the 1st step was gathering Korean vocabularies and building a databse for the translation of English terms of International Electronical Vocabulary(IEV) into Korean terms, the 2nd step was to find correct or proper Korean term which is in accord with each English term of IEV on the Electropedia. In this step, members of Korean TC 1 worked for search proper Korean terms using developed computer programs and databases which were made of Korean electronical dictionaries. After selection of proper terms, they did the cross-checking work for Korean terms each other. The last step was to register all of these Korean terms on the Electropedia. As a result, 20,766 Korean electronical terms were registered on the Electropedia in 2017. In the future, it is needed that the definition of English technical terms are translated into Korean.

• Journal of Information Management
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• 제40권3호
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• pp.151-176
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• 2009

The purpose of this study is to propose effective management plan for official seal guaranteeing authenticity of archival records. For this, this paper attempts to investigate current management conditions of central governments and National Archives. First, disclosure of information on official seal register in central government was requested. In addition, surveys and interviews with person in charge were carried out. Additionally, official seal lists of National Archives were analyzed and the person in charge was interviewed. Based on these, this paper proposed management plans of official seal such as a periodic inspection of management conditions, training programs for the person in charge, selective acquisition, reporting of the current state, improvement of law system, improvement of document formats, and establishment of an electronic seal management system, etc.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 1998년도 가을 학술발표논문집 Vol.25 No.2 (1)
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• pp.626-628
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• 1998

XML은 사용자가 각 응용에 따라 필요한 태그 집합과 문서 구조를 정의할 수 있는 효과적인 기반을 제공 하지만, 서로 다르게 정의되는 태그는 그 이름만으로는 정확한 의미를 식별하기가 어렵다. 본 논문에서는 데이터 레지스트리에 기반 하여 DTD를 작성함으로써 XML 태그에 문맥적인 의미를 부여하는 방법을 제시하였으며, 이를 지원하는 DTD 작성도구를 설계하였다. XML의 기능에 데이터 레지스트리가 제공하는 표준화된 의미를 추가시킴으로써 DTD에 독립적인 문서 교환이 가능하며, 태그의 의미를 이용한 문서의 검색을 효과적으로 수행할 수 있다.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (1)
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• pp.316-318
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• 2004

유비쿼터스 네트워크의 보안요구사항을 살펴보면 센서의 위치, 저 전력으로 인한 성능의 제약, 브로트 캐스팅에 의한 통신 등 들 수 있다. 그 중이 논문에서는 저 전력으로 인한 성능의 제약측면을 고려한 상호인증 (Mutual Authentication)프로토콜을 새롭게 제안한다. 상호인증 프로토콜은 RM(Register Manager)와 AM(Authentication Manager)로 구성되며 RM과 AM을 통해 각 센서 노드들의 한정된 전력문제를 해결하였고 가 각 센서노드에서의 메시지의 길이와 오퍼레이션 수를 최소화함으로 전력 낭비를 해결하였다. 또한 제안하는 프로토콜은 센서노드간의 상호인증을 통한 세션키 분배를 통해 안전한 통신이 가능하다.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (1)
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• pp.322-324
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• 2004

보안 시스템은 암호화 기능을 필요로 하고 암호화를 위 한 비밀키로 난수를 사용한다 난수 발생기에는 순수 난수 발생기와 의사 난수 발생기가 있다. 본 논문에서는 펜티엄부터 인텔 프로세서들이 가지고 있는 타임스탬프 카운터 레지스터(TSC MSR)에서 시드를 가져와 비트 가공을 통해 난수를 발생하는 난수 발생기를 구현하였다. 구현된 난수 발생기의 난수 품질을 평가하기 위해 순수 난수 발생기, 의사 난수 발생기의 난수 시퀀스와 비교하였다. 구현된 난수 발생기가 생성한 난수 시퀀스는 순수 난수 발생기의 난수 시퀀스와 큰 차이가 없고 특정 디바이스 없이 응용이 간단하다는 점에서 보안 시스템의 암호화키로 사용하기에 적합하다.

• Proceedings of the Korean Information Science Society Conference
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• 한국정보과학회 1999년도 가을 학술발표논문집 Vol.26 No.2 (1)
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• pp.400-402
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• 1999

그래프 분할을 사용한 레지스터 할당과 Chaitin의 레지스터 할당 방법의 성능을 비교하였다. 실험 데이터로 Appel이 제시한 간섭 그래프를 사용하였고, 각 알고리즘에서 요구되는 최소 레지스터 수를 비교하였다. 그 결과 그래프 분할을 사용한 방법에서 더 적은 수의 레지스터가 요구되었다. 가용 레지스터가 제한되어 있는 경우, 레지스터 요구 수가 감소되면 삽입되는 대피 코드의 수도 감소된다. 대피 코드의 발생이 줄어들면 메모리를 참조하는 인스트럭션의 수가 감소하여 실행시간을 단축시킬 수 있다. 따라서 컴파일러의 최적화 단계에서 그래프 분할 방법을 사용한 레지스터 할당으로 성능 향상을 기대할 수 있다.