• ETRI Journal
• /
• 제25권5호
• /
• pp.321-327
• /
• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• 한국콘텐츠학회논문지
• /
• 제5권1호
• /
• pp.229-236
• /
• 2005

System-On-a-Chip(SOC)을 테스트하는 동안에 요구되는 테스트 시간과 전력소모는 SOC내의 IP 코어의 개수가 증가함에 따라서 매우 중요하게 되었다. 본 논문에서는 수정된 스캔 래치 재배열을 사용하여 scan-in 전력소모와 테스트 데이터의 양을 줄일 수 있는 새로운 알고리즘을 제안한다. 스캔 벡터 내의 해밍거리를 최소화하도록 스캔 래치 재배열을 적용하였으며 스캔 래치 재배열을 하는 동안에 스캔 벡터 내에 존재하는 don't care 입력을 할당하여 저전력 및 테스트 데이터 압축을 하였으며 ISCAS 89 벤치마크 외호에 적용하여 모든 경우에 있어서 테스트 데이터를 압축하고 저전력 스캔 테스팅을 구현하였다.

• 대한전기학회논문지:시스템및제어부문D
• /
• 제49권11호
• /
• pp.637-642
• /
• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• 대한전기학회논문지:전력기술부문A
• /
• 제48권9호
• /
• pp.1161-1166
• /
• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• 한국컴퓨터정보학회논문지
• /
• 제3권2호
• /
• pp.105-112
• /
• 1998

본 논문에서는 다중 보드를 시험하기 위한 새로운 구조인 확장된 스캔 경로(ESP: Extended Scan Path) 구조를 제안한다. 보드를 시험하기 위한 기존의 구조로는 단일 스캔경로와 다중 스캔 경로가 있다. 단일 스캔경로 구조는 시험 데이타의 전송 경로인 스캔 경로가 하나로 연결되므로 스캔 경로가 단락이나 개방으로 결함이 생기면 나머지 스캔 경로에올바른 시험 데이타를 입력할 수 없다. 다중 스캔 경로 구조는 다중 보드 시험 시 보드마다별도의 신호선이 추가된다 그러므로 기존의 두 구조는 다중 보드 시험에는 부적절하다. 제안된 ESP 구조를 단일 스캔 경로 구조와 비교하면, 스캔 경로 상에 결함이 발생하더라도 그 결함은 하나의 스캔 경로에만 한정되어 다른 스캔 경로의 시험 데이타에는 영향을 주지않는다. 뿐만 아니라, 비스트 (BIST: Built In Self Test)와 IEEE 1149.1 경계면 스캔 시험을 병렬로 수행함으로써 시험에 소요되는 시간을 단축한다. 본 논문에서는 제안한 ESP 구조와 기존 시험 구조의 성능을 비교하기 위해서 수치적 비교를 한다.

• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2011년도 추계학술대회
• /
• pp.892-895
• /
• 2011

SoC(System-On-Chip)을 테스트 하는 동안 소모하는 전력소모는 SoC내의 IP 코어가 증가됨에 따라 매우 중요한 요소가 되었다. 본 논문에서는 Scan Latch Reordering과 Clock Gating 기법을 적용하여 scan-in 전력소모를 줄이는 알고리즘을 제안한다. Scan vector들의 해밍거리를 최소로 하는 새로운 Scan Latch Reordering을 적용하였으며 Gated scan 셀을 사용하여 저전력을 구현하였다. ISCAS 89 벤치마크 회로에 적용하여 실험한 결과 모든 회로에 대하여 향상된 전력소모를 보였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 제38회 하계학술대회
• /
• pp.1850-1851
• /
• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• ETRI Journal
• /
• 제30권3호
• /
• pp.412-420
• /
• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2007년도 제38회 하계학술대회
• /
• pp.1840-1841
• /
• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• ETRI Journal
• /
• 제25권3호
• /
• pp.187-194
• /
• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.