References
- Proc. of IEEE Int'l Test Conf. Delay Test Generation. Ⅱ. Algebra and Algorithms Iyengar, V.S.;Rosen, B.K.;Spillinger, I.
- Proc. of IEEE Int'l Test Conf. Model for Delay Faults Based upon Paths Smith, G.L.
- Proc. of IEEE Int'l Conf. on Computer-Aided Design An Automatic Test Pattern Generator for the Detection of Path Delay Faults Reddy, S.;Lin, C.;Patel, S.
- IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems On Path Selection in Combinational Logic Circuits Li, W.;Reddy, S.;Sahni, S.
- IEEE Trans. on VLSI Line Coverage of Path Delay Faults Majhi, A.;Agrawal, V.;Jacob, J.;Patnaik, L.
- Proc. of IEEE Int'l Test Conf. Selection of Potentially Testable Path Delay Faults for Test Generation Murakami, A.;Kajihara, S.;Sasao, T.;Pomeranz, R.;Reddy, S.
- Proc. of IEEE Int'l Test Conf. Finding a Small Set of Longest Testable Paths that Cover Every Gate Sharma, M.;Patel, J.
- IEEE Trans. on Computer-Aided Design On Delay Fault Testing in Logic Circuits Lin, C.;Reddy, S.
- Proc. of IEEE Int'l Symp. on Fault-Tolerant Computing An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability and Serviceability Dasgupta, S.;Walther, R.;Williams, T.
- Proc. of IEEE Design Automation Conf. Equivalence of Robust Delay-fault and Single Stuck-fault Test Generation Saldanha, A.;Brayton, R.;Sangiovanni-Vicentelli, A.
- Proc. of IEEE Int'l Test Conf. Delay Testing for Non-robust Untestable Circuits Cheng, K.T.;Chen, H.
- Proc. of IEEE/ACM Design Automation Conf. Delay Fault Coverage and Performance Tradeoffs Lam, W.;Saldanha, A.;Brayton, R.;Sangiovanni-Vicentelli, A.
- IEEE Trans. on Computers Synthesis of Delay-Verifiable Combinational Circuits Ke, W.;Menon, P.
- IEEE Trans. on Computer-Aided Design Synthesis of Robust Delay-Fault-Testable Circuits: Practice Devadas, S.;Keutzer, K.
- IEEE Trans. on Computer-Aided Design Validatable Non-Robust Delay-Fault-Testable Circuits via Logic Synthesis Devadas, S.;Keutzer, K.
- IEEE Trans. on Computers An Experimental Delay Test Generator for LSI logic Lesser, J.D.;Schedletsky, J.J.
- IEEE Trans. on Computers Test Pattern Generation for Path Delay Faults using Binary Decision Diagrams Bhattacharya, D.;Agrawal, P.;Agrawal, V.D.
- Proc. of Design Automation Conf. Test Generation for Path Delay Faults Based on Satistiability Cheng, C.A.;Gupta, S.K.
- Proc. of EURO-DAC Path Delay ATPG for Standard Scan Design Wittmann, H.;Henftling, M.
- ETRI J. v.23 no.3 Efficient Path Delay Test Generation for Custom Designs Kang, Sung-Ho;Underwood, Bill;Law, Wai-On;Konuk, Haluk
- Proc. of Int'l Conf. on Computer Design Path-Delay Fault Simulation for a Standard Scan Design Methodology Kang, S.;Law, W.;Underwood, B.
- Proc. of IEEE Int'l Symp. on Fault Tolerant Computing Advanced Automatic Test Pattern Generation Techniques for Path Delay Faults Schulz, M.H.;Fuchs, K.;Fink, F.
- IEEE Design and Test of Computers Generating Tests for Delay Faults in Nonscan Circuits Agrawal, P.;Agrawal, V.D.;Seth, S.C.
- Proc. of IEEE Asian Test Symp. An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing Hsu, Y.C.;Gupta, S.K.
- Proc. of IEEE Int'l Test Conf. Delay Testing with Clock Control: An Alternative to Enhanced Scan Tekumalla, R.C.;Menon, P.R.
- IEEE Trans. on Integrated Circuits and Systems On Variable Clock Methods for Path Delay Testing of Sequential Circuits Chakraborty, T.J.;Agrawal, V.D.;Bushnell, M.L.
- Proc. of IEEE VLSI design Path Delay Testing: Variable-Clock Versus Rated-Clock Majumder, S.;Agrawal, V.D.;Bushnell, M.L.
- Proc. of Asian Test Symp. Design for Hierarchical Two-pattern Testability of Data Paths Altaf-Ul-Amin Md.;Ohtake, S.;Fujiwara, H.
- Proc. of EURO-DAC DynaTAPP: Dynamic Timing Analysis with Partial Path Activation In Sequential Circuits Agrawal, P.;Agrawal, V.D.;Seth, S.C.