• ETRI Journal
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• v.25 no.5
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• pp.321-327
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• 2003

Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.11
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• pp.637-642
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• 2000

IEEE 1149.1 boundary scan architecture is used as a standard in board-level system testing. The simplicity of this architecture is an advantage in system testing, but at the same time, it it makes a limitation of applications. Because of several problems such as 3-state net conflicts, or ambiguity issues, interconnect testing for multi-drop multi-board systems is more difficult than that of single board systems. A new approach using IEEE 1149.1 boundary scan architecture for multi-drop multi-board systems is developed in this paper. Adding boundary scan cells on backplane bus lines, each board has a complete scan-chain for interconnect test. This new scan-path insertion method on backplane bus using limited 1149.1 test bus less area overhead and mord efficient than previous approaches.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1161-1166
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• 1999

Delay testing has become highlighted in the field of digital circuits as the speed and the density of the circuits improve greatly. However, delay faults in sequential circuits cannot be detected easily due to the existence of state registers. To overcome this difficulty a new scan filp-flop is devised which can be used for both stuck-at testing and delay testing. In addition, the new scan flip-flop can be applied to both the existing functional justification method and the newly-developed reverse functional justification method which uses scan flip-flops as storing the second test patterns rather than the first test patterns. Experimental results on ISCAS 89 benchmark circuits show that the number of testable paths can be increased by about 10% on the average.

• Journal of the Korea Society of Computer and Information
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• v.3 no.2
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• pp.105-112
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• 1998

In this paper, we propose a ESP(Extended Scan Path) architecture for multi-board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan path is either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using the proposed ESP architecture, we observed that the test time is short compared with the single scan path architecture. By comparing the ESP architecture with single scan path responding to independency of scan path, test time and with multi-scan path responding to signal, synchronization, we showed that the architecture has improved results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.892-895
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• 2011

Power consumption during testing System-On-Chip (SOC) are becoming increasingly important as the IP core increases in SOC. We present a new algorithm to reduce the scan-in power using the modified scan latch reordering and clock gating. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power. Also, we apply the clock gated scan cells. Experimental results for ISCAS 89 benchmark circuits show that reduced low power scan testing can be achieved in all cases.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1850-1851
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• ETRI Journal
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• v.30 no.3
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1840-1841
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• 2007

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.