• Publications of The Korean Astronomical Society
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• v.8 no.1
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• pp.33-45
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• 1993

The variation of instrumental profile for the different scan speed of PDS is estimated as FWHM of the assumed Gaussian Profile. The effects of scan speed and scan aperture of PDS on the objective prism spectrum analysis are investigated for 8 combinations of scan speed and scan aperture. Amomg them. D1 apture with 15 csu is found to be the most optimum choice for measuring KISO objective prism film. We suggest the preliminary test study of the scan speed and aperture for the optimum use of PDS for any massive scan of spectra. The optimum scan speed and aperture depends on the dispersion of spectrum as well as the type of phtographic emulsion.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.572-580
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• 1996

This paper describes a test generation method for sequential circuits which improves the application limits of the IPMT method by applying the partial scan design to the IPMT method. To solve the problem that the IPMT method requires enormous computation time in image computation, and generates test patterns after the partialscan design is introduced to reduce test complexity. Scan flip-flops are selected for the partial scan design according to the node size of the state functions of a sequential circuit in their binary decision diagram representations. Experimental results on ISCAS'95 benchmark circuits show that a test generator based on our method has achieved 100% fault coverage by use of either 20% scan FFs for s344, s349, and s420 or 80% scan FFs for sl423. However, test gener-ators based on the previous IPM method have not achieved 100% fault coverage for those circuits.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.74-79
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• 2006

Test Interface Controller (TIC) provided by ARM Ltd. is widely used for functional testing of System-on-Chip (SoC) adopting Advanced Microcontroller Bus Architecture (AMBA) bus system. Accordingly, this architecture has a deficiency of not being able to concurrently shifting in and out the structural scan test patterns through the TIC and AMBA bus. This paper introduces a new AMBA based Test Access Mechanism (ATAM) for speedy testing of SoCs embedding ARM cores. While preserving the compatability with the ARM TIC, since scan in and out operations can be performed simultaneously, test application time through the expensive Automatic Test Equipment (ATE) can be drastically reduced.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.12
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• pp.25-31
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• 2018

Selective Laser Melting is one of the representative 3D printing techniques for handling metal materials. The main factors influencing the characteristics of structures fabricated by the SLM method include the build-up angle of structures, laser power, laser scan speed, and scan spacing. In this study, the tensile properties of AlSi10Mg alloys were investigated by considering the build-up angle of tensile test specimens, laser scanning speed and scan spacing as variables. The yield stress, tensile strength, and elongation were considered as tensile properties. From the test results, it was confirmed that the yield stress values were lowered in the order of 0, 45, and 90 based on the manufacturing direction of the tensile specimen. The maximum yield stress value was obtained at 1870 mm / min based on the laser scan speed. The yield stress size decreased with decreasing scan speed. Based on the laser scan spacing, as the value increases, the yield stress increases, but the variation is smaller than the other test criteria. The tendency of the tensile strength and elongation variation depending on the test conditions was difficult to understand.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.11
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• pp.54-61
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for controller circuits is proposed. The proposed method always guarantees a short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The proposed method also shortens the test application time through a test pattern re-ordering procedure. The efficiency of the proposed method is demonstrated using well known MCNC'91 FSM benchmark circuits.

• Journal of Internet Computing and Services
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• v.4 no.3
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• pp.31-37
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• 2003

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC'91 FSM benchmark circuits.

• Korean Journal of Bronchoesophagology
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• v.5 no.1
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• pp.55-61
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• 1999

The authors recently experienced a case of ectopic thyroid. A 15-year-old female patient visited to ENT department with the complaint of the submental neck mass. On physical examination, the mass was relatively firm, non tender and 3$\times$2cm in size. Oral cavity examination revealed 0.5$\times$0.5cm sized pink colored mass near the foramen cecum area. Suspecting ectopic thyroid, thyroid function test, thyroid scan, neck computed tomogram scan were performed. Thyroid scan revealed a functioning thyroid on the lingual and submental area without normal uptake in the anterior neck area. Thyroid (unction test was normal. Pre-contrast computed tomogram scan revealed an ectopic thyroid in the lingual and submental area. A review of literature concerning ectopic thyroid was discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.9-16
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• 2004

For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.197-200
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• 2002

We newly developed the procedures of X-ray Cargo inspection system with acquisition of multi-channel data, analog to digital converter and post logic circuit which is controlled by the FPGA. The IEEE1149.1 standard defines a four-wire serial interface(a fifth wire is optional)to access complex integrated circuits(ICs) such as PLD. This paper describes that Boundary_Scan test method applied to our home made cargo inspection system.