• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.1957-1958
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the simulator and algorithm that judges whether Tri-state Bus lines is the circuit which have X-value or One-hot Value after presuming the control signal of the lines which output X-value in the logic circuit to solve the most serious problems.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.71-74
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+PlusII and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.11-23
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats into a target format. Circuits for the conversion have been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL, simulated on Max+plus Ⅱ , and implemented with an FPGA chip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation techniques according to simulation results and implementation.

• Proceedings of the Korea Society for Simulation Conference
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• 2000.04a
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• pp.91-95
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• 2000

The purpose of format conversion is to convert a wide range of personal computer video formats to a target format. Circuits for the conversion has been developed by means of interpolation techniques, such as zero-order interpolation, bilinear interpolation, and bisigmoidal interpolation. This paper proposes a scan converter using cubic splines. The converter was modeled in VHDL on Max+Plus II and implemented with an FPGA cpip. The circuit gives much better conversion performance than a scan converter with zero-order or linear interpolation.

• ETRI Journal
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• v.25 no.3
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• pp.187-194
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• 2003

Delay testing has become an area of focus in the field of digital circuits as the speed and density of circuits have greatly improved. This paper proposes a new scan flip-flop and test algorithm to overcome some of the problems in delay testing. In the proposed test algorithm, the second test pattern is generated by scan justification, and the first test pattern is processed by functional justification. In the conventional functional justification, it is hard to generate the proper second test pattern because it uses a combinational circuit for the pattern. The proposed scan justification has the advantage of easily generating the second test pattern by direct justification from the scan. To implement our scheme, we devised a new scan in which the slave latch is bypassed by an additional latch to allow the slave to hold its state while a new pattern is scanned in. Experimental results on ISCAS'89 benchmark circuits show that the number of testable paths can be increased by about 45 % over the conventional functional justification.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• Journal of the Korea Society of Computer and Information
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• v.13 no.4
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• pp.87-95
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• 2008

In this paper, we developed a selectable observation Point test architecture and test procedure for clocked 4-bit synchronous counter circuit based on boundary scan architecture. To develope, we analyze the operation of Sample/Preload instruction on boundary scan architecture. The Sample/Preload instruction make Possible to snapshot of outputs of CUT(circuit under test) at the specific time. But the changes of output of CUT during normal operation are not possible to observe using Sample/Preload in typical scan architecture. We suggested a selectable observation point test architecture that allows to select output of CUT and to observe of the changes of selected output of CUT during normal operation. The suggested a selectable observation point test architecture and test procedure is simulated by Altera Max 10.0. The simulation results of 4-bit counter shows the accurate operation and effectiveness of the proposed test architecture and procedure.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.4
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• pp.210-215
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• 2004

This paper proposes an implicit method for computing the minimum cost feedback vertex set for a graph. For an arbitrary graph, a Boolean function is derived, whose satisfying assignments directly correspond to feedback vertex sets of the graph. Importantly, cycles in the graph are never explicitly enumerated, but rather, are captured implicitly in this Boolean function. This function is then used to determine the minimum cost feedback vertex set. Even though computing the minimum cost satisfying assignment for a Boolean function remains an NP-hard problem, it is possible to exploit the advances made in the area of Boolean function representation in logic synthesis to tackle this problem efficiently in practice for even reasonably large sized graphs. The algorithm has obvious application in flip-flop selection for partial scan. The algorithm proposed in this paper is the first to obtain the MFVS solutions for many benchmark circuits.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.7
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• pp.32-39
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• 1999

Digital signal processor (DSP) is used to obtain the peak value and the time difference of ultrasonic signals, to make digital filter, and to derive mathematical transformation from analog circuit. In this study, C-scan system and control program have been developed to high speed data acquisition. This system consists of signal processing parts (DSP, oscilloscope, pulser/receiver, digitizer), scanner, and control program. The developed system has been applied to a practical ultrasonic testing in overlay weld, and demonstrated high speed with precision