• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.141-148
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• 2012

A design of a 32-bit fourth-stage decimation filter decimation filter used in sigma-delta analog-to-digital (A/D) converter is proposed in this work. A four-stage decimation filter with down-sampling factor of 512 and 32-bit output is developed. A multi-stage cascaded integrator-comb (CIC) filter, which reduces the sampling rate by 64, is used in the first stage. Three half-band FIR filters are used after the CIC filter, each of which reduces the sampling rate by two. The pipeline structure is applied in the CIC filter to reduce the power consumption of the CIC. The Canonic Signed Digit (CSD) arithmetic is used to optimize the multiplier structure of the FIR filter. This filter is implemented based on a semi-custom design flow and a 130nm CMOS standard cell library. This decimation filter operates at 98.304 MHz and provides 32-bit output data at an audio frequency of 192 kHz with power consumption of $697{\mu}W$. In comparison to the previous work, this design shows a higher performance in resolution, operation frequency and decimation factor with lower power consumption and small logic utilization.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.404-416
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• 2015

Small-area, low-power coarse and fine frequency detectors (FDs) are proposed for an adaptive bandwidth referenceless CDR with a wide range of input data rate. The coarse FD implemented with two flip-flops eliminates harmonic locking as long as the initial frequency of the CDR is lower than the target frequency. The fine FD samples the incoming input data by using half-rate four phase clocks, while the conventional rotational FD samples the full-rate clock signal by the incoming input data. The fine FD uses only a half number of flip-flops compared to the rotational FD by sharing the sampling and retiming circuitry with PLL. The proposed CDR chip in a 65-nm CMOS process satisfies the jitter tolerance specifications of both USB 3.0 and USB 3.1. The proposed CDR works in the range of input data rate; 2 Gb/s ~ 8 Gb/s at 1.2 V, 4 Gb/s ~ 11 Gb/s at 1.5 V. It consumes 26 mW at 5 Gb/s and 1.2 V, and 41 mW at 10 Gb/s and 1.5 V. The measured phase noise was -97.76 dBc/Hz at the 1 MHz frequency offset from the center frequency of 2.5 GHz. The measured rms jitter was 5.0 ps at 5 Gb/s and 4.5 ps at 10 Gb/s.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.249-251
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• 2022

In this paper, we present machine learning to control drone flight using EEG signals. We defined takeoff, forward, backward, left movement and right movement as control targets and measured EEG signals from the frontal lobe for controlling using Fp1. Fp2 Fp2 two-channel dry electrode (NeuroNicle FX2) measuring at 250Hz sampling rate. And the collected data were filtered at 6~20Hz cutoff frequency. We measured the motion image of the action associated with each control target open for 5.19 seconds. Using Matlab's classification learner for the measured EEG signal, the triple layer neural network, logistic regression kernel, nonlinear polynomial Support Vector Machine(SVM) learning was performed, logistic regression kernel was confirmed as the highest accuracy for takeoff and forward, backward, left movement and right movement of the drone in learning by class True Positive Rate(TPR).

• The Journal of the Acoustical Society of Korea
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• v.42 no.5
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• pp.403-411
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• 2023

Functional ultrasound imaging, such as elasticity imaging and micro-blood flow Doppler imaging, enhances diagnostic capability by providing useful mechanical and functional information about tissues. However, the implementation of functional ultrasound imaging poses limitations such as the storage of vast amounts of data in Radio Frequency (RF) data acquisition and processing. In this paper, we propose a sub-Nyquist approach that reduces the amount of acquired axial samples for efficient shear-wave elasticity imaging. The proposed method acquires data at a sampling rate one-third lower than the conventional Nyquist sampling rate and tracks shear-wave signals through RF signals reconstructed using band-pass filtering-based interpolation. In this approach, the RF signal is assumed to have a fractional bandwidth of 67 %. To validate the approach, we reconstruct the shear-wave velocity images using shear-wave tracking data obtained by conventional and proposed approaches, and compare the group velocity, contrast-to-noise ratio, and structural similarity index measurement. We qualitatively and quantitatively demonstrate the potential of sub-Nyquist sampling-based shear-wave elasticity imaging, indicating that our approach could be practically useful in three-dimensional shear-wave elasticity imaging, where a massive amount of ultrasound data is required.

• The Journal of the Acoustical Society of Korea
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• v.21 no.6
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• pp.566-575
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• 2002

Low-titrate audio coding enables a number of Internet and mobile multimedia streaming service more efficiently. For the help of next-generation mobile telephone technologies and digital audio/video compression algorithm, we can enjoy the real-time multimedia contents on our mobile devices (cellular phone, PDA notebook, etc). But the limited available bandwidth of mobile communication network prohibits transmitting high-qualify AV contents. In addition, most bandwidth is assigned to transmit video contents. In this paper, we design a novel and simple method for reproducing high frequency components. The spectrum of high frequency components, which are lost by down-sampling, are modeled by the energy rate with low frequency band in Bark scale, and these values are multiplexed with conventional coded bitstream. At the decoder side, the high frequency components are reconstructed by duplicating with low frequency band spectrum at a rate of decoded energy rates. As a result of segmental SNR and MOS test, we convinced that our proposed method enhances the subjective sound quality only 10%∼20% additional bits. In addition, this proposed method can apply all kinds of frequency domain audio compression algorithms, such as MPEG-1/2, AAC, AC-3, and etc.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.4
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• pp.703-719
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• 2011

In multi-user wireless communication systems, adaptive modulation and scheduling are promising techniques for increasing the system throughput. However, a mass of wireless recourse will be occupied and spectrum efficiency will be decreased to feedback channel quality indication (CQI) of all users in every subcarrier or chunk for adaptive orthogonal frequency division multiplexing (OFDM) systems. Thus numerous limited feedback schemes are proposed to reduce the system overhead. The recently proposed compressive sensing (CS) theory provides a new framework to jointly measure and compress signals that allows less sampling and storage resources than traditional approaches based on Nyquist sampling. In this paper, we proposed two novel CQI feedback schemes based on general CS and subspace CS, respectively, both of which could be used in a wireless OFDM system. The feedback rate with subspace CS is greatly decreased by exploiting the subspace information of the underlying signal. Simulation results show the effectiveness of the proposed methods, with the same feedback rate, the throughputs with subspace CS outperform the discrete cosine transform (DCT) based method which is usually employed, and the throughputs with general CS outperform DCT when the feedback rate is larger than 0.13 bits/subcarrier.

• ETRI Journal
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• v.26 no.6
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• pp.555-559
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• 2004

We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.170-172
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• 2005

The DSD(Direct Stream Digital) encoder, which is a standard for SACD(Super Audio Compact Disc) proposed by Sony and philips, use 1 bit representation with a sampling frequency of 2.8224 MHz (64 $\times$ 44.1 kHz). For multi-rate PCM (Pulse Code Modulation) input like as 48/96/192 kHz, a external sample-rate converter is necessary to the DSD encoder. This paper has been proposed a digital filter structure composed of sample-rate converter and interpolation filter for the DSD encoder with multi-rate (48/96/192 kHz) PCM input. without a external sample-rate converter.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.358-360
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• 2005

The DSD(Direct Stream Digital) encoder, which is a standard for SACD(Super Audio Compact Disc) proposed by Sony and philips, uses 1 bit representation with a sampling frequency of 2.8224MHz (64${\times}$44.1kHz). For multi-rate PCM (Pulse Code Modulation) input such as 8${\sim}$192kHz, a external sample-rate converter is necessary to the DSD encoder. This paper has been proposed a digital mter structure composed of sample-rate converter and interpolaton filter for the DSD encoder with multi-rate (8${\sim}$192kHz) PCM input, without a external sample-rate converter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.