• 센서학회지
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• 제5권1호
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• pp.71-77
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• 1996

마이크로머시닝의 구조재료인 다결정 Si이 희생산화막의 영향을 받음을 고려하여 다결정 Si을 열산화시킨 다결정-산화막을 새로운 희생산화막의 재료로서 제안하고 평가하였다. 다결정-산화막상에 성장시킨 다결정 Si은 통상의 희생산화막상에 성장시키는 경우보다 grain size가 증가하였고, XRD결과를 통해 (111) texture의 증가와, 부가적인 (220) texture가 형성됨을 관찰하였다. 또한, 다결정-산화막상에 성장시킨 다결정 Si의 경우, 그 응력이 작고 균일한 분포를 나타내었다.

• 한국전기전자재료학회논문지
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• 제17권4호
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• pp.373-377
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• 2004

We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

• 한국전기전자재료학회논문지
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• 제29권7호
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• pp.435-439
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• 2016

We developed a Ag nanowire patterning technique using a water-soluble sacrificial layer. To form a water-soluble sacrificial layer, germanium was deposited on the substrate and then water-soluble germanium oxide was simply formed by thermal oxidation of germanium using a conventional furnace. The formation of Ag nanowire patterns with various line and space arrangements was successfully demonstrated using this patterning process. The main advantage of this patterning technique is that it does not use a strong acid etchant, thereby preventing damage to the Ag nanowire during the patterning process.

• 센서학회지
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• 제8권5호
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• pp.414-420
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• 1999

희생층을 제거하는 기술은 표면 마이크로머시닝 공정의 핵심기술중 하나이다. 그러나 희생층을 제거하는데 널리 쓰이는 BHF 용액을 포함한 HF 수용액은 희생층 제거시 금속층으로 쓰이는 알루미늄도 같이 식각하는 것으로 알려져 있다. 기존의 문헌에서 $NH_4F$:HF:glycerine=4:1:2의 비를 갖는 혼합 용액이 알루미늄과 PSG 간의 식각 선택비가 최적조건으로 제시되었지만 이 희생층 식각액 또한 상당한 알루미능 식각률을 가지고 있다. 본 논문에서는 HF, $NH_4F$, glycerine의 농도를 광범위하게 변화시켜 희생층 제거에 필요한 최적 혼합비를 개발하였으며 그 결과 $NH_4F$:HF:glycerine=2:1:4의 혼합비에서 약 7,700정도의 PSG와 Al의 식각 선택비를 가져 기존의 최적 식각 선택비보다 차수가 약 6배정도 향상된 희생층 식각액을 얻을 수 있었다. 이 조건에서 PSG의 식각률은 희생층 제거시 충분히 빠른 값인 약 $2.1\;{\mu}m/min$을 나타내었다. 이러한 개발된 희생층 식각액은 표면 마이크로머시닝 공정에서 알루미늄 금속 공정의 추가를 용이하게 한다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.2001-2003
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• 1996

In this study, Allied Signal 211 SOG was used as a sacrificial material. After researching its etching properties, we adapted it to bottom-drive micrometers. SOG was superior etch rate and roughness to them of PSG or CVD-oxide and possible to low-temperature processing. Etching properties of SOG depended on the temperature and duration of its bake and cure. SOG used in the fabrication of bottom-drive micrometers showed us usefulness as a sacrificial layer and haying a least influence on machines on it in comparison with conventional sacrificial materials.

• 전자공학회논문지
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• 제51권2호
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• pp.33-37
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• 2014

본 논문에서는 AlGaN/GaN HFET의 누설전류 특성을 개선하고자 산화갈륨 희생층 공정을 이용한 새로운 패시베이션 공정을 제안하였다. 오믹 전극 형성시 고온 열처리 과정으로 인해 갈륨의 표면 손상이 불가피하다. 표면 손상을 방지하기 위해 보편적으로 선표면처리 공정을 사용하기도 하지만 이러한 방법만으로는 표면 손상을 완전히 없애기 어렵다. 본 연구에서 새롭게 제안된 산화갈륨 희생층을 이용한 공정 방법은 고온 열처리 후 손상된 표면에 $O_2$ 플라즈마 처리를 통해 산화갈륨층을 형성한 뒤, 염화수소를 이용하여 산화갈륨층을 식각한다. 우수한 상태의 표면 상태를 얻을 수 있었으며, 누설전류의 확연한 감소로 subthreshold slope이 개선되었을 뿐만 아니라 최대 드레인 전류 특성도 594 mA/mm에서 634 mA/mm로 증가하였다. 질화갈륨 희생층 공정의 효과를 분석하기 위해 X-선 광전자 분광법을 이용하여 질화갈륨의 표면 변화에 대해 살펴보았다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.83-83
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• 2008

Metal-oxide-silicon-on-insulator (MOSOI) structures were fabricated to study the effect caused by reactive ion etching (RIE) and sacrificial oxidation process on silicon-on-insulator (SOI) layer. The MOSOI capacitors with an etch-damaged SOI layer were characterized by capacitance-voltage (C-V) measurements and compared to the sacrificial oxidation treated samples and the reference samples without etching treatment. The measured C-V curves were compared to the numerical results from 2-dimensional (2-D) simulations. The measurements revealed that the profile of C-V curves significantly changes depending on the SOI surface condition of the MOSOI capacitors. The shift in the measured C-V curves, due to the difference of the fixed oxide charge ($Q_f$), together with the numerical simulation analysis and atomic force microscopy (AFM) analysis, allowed extracting the fixed oxide charges ($Q_f$) in the structures as well as 2-D carrier distribution profiles.

• 센서학회지
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• 제32권5호
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• pp.328-333
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• 2023

This study experimentally verified the etch rate of the SiO₂ sacrificial layer etching process with a single etch hole using vapor-phase hydrogen fluoride (VHF) etching. To fabricate small-sized polysilicon etch holes, both circular and triangular pattern masks were employed. Etch holes were fabricated in the polysilicon thin film on the SiO₂ sacrificial layer, and VHF etching was performed to release the polysilicon thin film. The lateral etch rate was measured for varying etch hole sizes and sacrificial layer thicknesses. Based on the measured results, we obtained an approximate equation for the etch rate as a function of the etch hole size and sacrificial layer thickness. The etch rates obtained in this study can be utilized to minimize structural damage caused by incomplete or excessive etching in sacrificial layer processes. In addition, the results of this study provide insights for optimizing sacrificial layer etching and properly designing the size and spacing of the etch holes. In the future, further research will be conducted to explore the formation of structures using chemical vapor deposition (CVD) processes to simultaneously seal etch hole and prevent adhesion owing to polysilicon film vibration.

• 센서학회지
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• 제24권6호
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• pp.379-384
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• 2015

An infrared image sensor is a core device in a thermal imaging system. The fabrication method of a focal plane array (FPA) is a key technology for a high resolution infrared image sensor. Each pixels in the FPA have $Si_3N_4/SiO_2$ membranes including legs to deposit bolometric materials and electrodes on Si readout circuits (ROIC). Instead of polyimide used to form a sacrificial layer, the feasibility of an amorphous silicon (${\alpha}-Si$) was verified experimentally in a $8{\times}8$ micro-bolometer array with a $50{\mu}m$ pitch. The elimination of the polyimide sacrificial layer hardened by a following plasma assisted deposition process is sometimes far from perfect, and thus requires longer plasma ashing times leading to the deformation of the membrane and leg. Since the amorphous Si could be removed in $XeF_2$ gas at room temperature, however, the fabricated micro-bolomertic structure was not damaged seriously. A radio frequency (RF) sputtered nickel oxide film was grown on a $Si_3N_4/SiO_2$ membrane fabricated using a low stress silicon nitride (LSSiN) technology with a LPCVD system. The deformation of the membrane was effectively reduced by a combining the ${\alpha}-Si$ and LSSiN process for a nickel oxide micro-bolometer.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.609-611
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• 1995

In this study, we experimented the properties of SOG film as sacrificials layers in surface micromachining and made $SiO_2$ films through spin, bake, cure process. When we culled SOG films once, SOG film thickness is 1000 $\sim$ 3000 ${\AA}$. Then we coaled 200-${\AA}$ SOG film on 9000 ${\AA}$-CVD oxide and then we fabricated test structure, cantilever and ring/beam structure. We estimated deformed structure by SEM. As the results, The deformation of the structure layer in the SOG-coated sacrificial layers is small compared with that or the structure layer on CVD oxide or PSG. In the future, we use multi coated SOG films, SOG film become adequate material as sacrificial layer.