• Title/Summary/Keyword: routing integrated

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A supply planning model based on inventory-allocation and vehicle routing problem with location-assignment (수송경로 문제를 고려한 물류최적화모델의 연구)

  • 황흥석;최철훈;박태원
    • Proceedings of the Korean Operations and Management Science Society Conference
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    • 1997.10a
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    • pp.201-204
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    • 1997
  • This study is focussed on optimization problems which require allocating the restricted inventory to demand points and assignment of vehicles to routes in order to deliver goods for demand sites with optimal decision. This study investigated an integrated model using three step-by-step approach based on relationship that exists between the inventory allocation and vehicle routing with restricted amount of inventory and transportations. we developed several sub-models such as; first, an inventory-allocation model, second a vehicle-routing model based on clustering and a heuristic algorithms, and last a vehicle routing scheduling model, a TSP-solver, based on genetic algorithm. Also, for each sub-models we have developed computer programs and by a sample run it was known that the proposed model to be a very acceptable model for the inventory-allocation and vehicle routing problems.

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A Vehicle Routing Model for Multi-Supply Centers Based on Lp-Distance (일반거리산정방법을 이용한 다-물류센터의 최적 수송경로 계획 모델)

  • Hwang, Heung-Suk
    • IE interfaces
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    • v.11 no.1
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    • pp.85-95
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    • 1998
  • This study is focussed on an optimal vehicle routing model for multi-supply centers in two-echelon logistic system. The aim of this study is to deliver goods for demand sites with optimal decision. This study investigated an integrated model using step-by-step approach based on relationship that exists between the inventory allocation and vehicle routing with restricted amount of inventory and transportations such as the capability of supply centers, vehicle capacity and transportation parameters. Three sub-models are developed: 1) sector-clustering model, 2) a vehicle-routing model based on clustering and a heuristic algorithm, and 3) a vehicle route scheduling model using TSP-solver based on genetic and branch-and-bound algorithm. Also, we have developed computer programs for each sub-models and user interface with visualization for major inputs and outputs. The application and superior performance of the proposed model are demonstrated by several sample runs for the inventory-allocation and vehicle routing problems.

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Job Deployment and Dynamic Routing for Container-AGVs (컨테이너용 AGV의 작업할당과 동적 경로계획)

  • So Myung-Ok;Lee Hyun-Sik;Jin Gang-Gyoo
    • Journal of Advanced Marine Engineering and Technology
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    • v.29 no.4
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    • pp.369-376
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    • 2005
  • In recent years, AGVs(Automated Guided Vehicles) have received growing attention as a subsystem of the integrated container operating system which enables unmanned control. improvement of job reliability, accuracy and productivity. Therefore, a number of works have been done to enhance the performance AGVs. In this paper. job deployment and a dynamic routing control system composed of supervisor, traffic controller. motion controller and routing table are discussed. A simple job deployment scheme and an efficient dynamic routing algorithm incorporating with the deadlock prediction and avoidance algorithm are investigated.

Performance Improvement on MPLS On-line Routing Algorithm for Dynamic Unbalanced Traffic Load

  • Sa-Ngiamsak, Wisitsak;Sombatsakulkit, Ekanun;Varakulsiripunth, Ruttikorn
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.1846-1850
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    • 2005
  • This paper presents a constrained-based routing (CBR) algorithm called, Dynamic Possible Path per Link (D-PPL) routing algorithm, for MultiProtocol Label Switching (MPLS) networks. In MPLS on-line routing, future traffics are unknown and network resource is limited. Therefore many routing algorithms such as Minimum Hop Algorithm (MHA), Widest Shortest Path (WSP), Dynamic Link Weight (DLW), Minimum Interference Routing Algorithm (MIRA), Profiled-Based Routing (PBR), Possible Path per Link (PPL) and Residual bandwidth integrated - Possible Path per Link (R-PPL) are proposed in order to improve network throughput and reduce rejection probability. MIRA is the first algorithm that introduces interference level avoidance between source-destination node pairs by integrating topology information or address of source-destination node pairs into the routing calculation. From its results, MIRA improves lower rejection probability performance. Nevertheless, MIRA suffer from its high routing complexity which could be considered as NP-Complete problem. In PBR, complexity of on-line routing is reduced comparing to those of MIRA, because link weights are off-line calculated by statistical profile of history traffics. However, because of dynamic of traffic nature, PBR maybe unsuitable for MPLS on-line routing. Also, both PPL and R-PPL routing algorithm we formerly proposed, are algorithms that achieve reduction of interference level among source-destination node pairs, rejection probability and routing complexity. Again, those previously proposed algorithms do not take into account the dynamic nature of traffic load. In fact, future traffics are unknown, but, amount of previous traffic over link can be measured. Therefore, this is the motivation of our proposed algorithm, the D-PPL. The D-PPL algorithm is improved based on the R-PPL routing algorithm by integrating traffic-per-link parameters. The parameters are periodically updated and are dynamically changed depended on current incoming traffic. The D-PPL tries to reserve residual bandwidth to service future request by avoid routing through those high traffic-per-link parameters. We have developed extensive MATLAB simulator to evaluate performance of the D-PPL. From simulation results, the D-PPL improves performance of MPLS on-line routing in terms of rejection probability and total throughput.

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Integrated Production-Distribution Planning for Single-Period Inventory Products Using a Hybrid Genetic Algorithm (혼성 유전알고리듬을 이용한 단일기간 재고품목의 통합 생산-분배계획 해법)

  • Park, Yang-Byung
    • IE interfaces
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    • v.16 no.3
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    • pp.280-290
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    • 2003
  • Many firms are trying to optimize their production and distribution functions separately, but possible savings by this approach may be limited. Nowadays, it is more important to analyze these two functions simultaneously by trading off the costs associated with the whole. In this paper, I treat a production and distribution planning problem for single-period inventory products comprised of a single production facility and multiple customers, with the aim of optimally coordinating important and interrelated decisions of production sequencing and vehicle routing. Then, I propose a hybrid genetic algorithm incorporating several local optimization techniques, HGAP, for integrated production-distribution planning. Computational results on test problems show that HGAP is effective and generates substantial cost savings over Hurter and Buer's decoupled planning approach in which vehicle routing is first developed and a production sequence is consequently derived. Especially, HGAP performs better on the problems where customers are dispersed with multi-item demand than on the problems where customers are divided into several zones based on single-item demand.

Stable Power Plan Technique for Implementing SoC (SoC 구현을 위한 안정적인 Power Plan 기법)

  • Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.16 no.12
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    • pp.2731-2740
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    • 2012
  • ASIC(application specific integrated circuit) process is a set of various technologies for fabricating a chip. Generally there have been many researches for RTL design, synthesis, floor plan & routing, low power scheme, clock tree synthesis, and testability which are widely researched in recent. In this paper we propose a new methodology of power strap routing in basis of design experience and experiment. First the power strap for vertical VDD and VSS and horizontal VDD and VSS is routed, and then after the problems which are generated in this process are analyzed, we propose a new process for resolving them. For this, the strap guide is inserted to protect the unnecessary strap routing and dumped for next steps. Next the unnecessary power straps which are generated the first inserting process are removed, and the pre-routing is performed for the macro cells. Finally the resultant power straps are routed using the dumped routing guide. Through the proposed process we identified the efficient and stable route of the power straps.

Dynamic resource reservation scheme for connection rerouting on ATM-based PCN (ATM-based PCN에서의 연결재라우팅을 위한 유선망자원 예약방안)

  • 장경훈;심재정;김덕진;강경훈
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.2
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    • pp.11-20
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    • 1997
  • It is a recent trend that mobile communications and PCS are intergrated into the broadband network. Broadband mutlimedia traffic will be transported over the integrated network. In this paper, we propose a connection re-routing method for fast inter-switch hadoffs and dynamic resurce reservation scheme, which is based on the proposed re-routing method, for the ATM-based personal communications network. To reduce the delay for re-routing method, for the ATM-based personal communications network. To reduce the delay for re-routing, the proposed re-routing method is to reserve VPI/VCIs for possible inter-swich handoff calls in advance. Our reservation scheme is to statistically reserve the fixed resources for possible inter-switch handoff calls, according to the QoS of the handoff calls. The simmulation reslts show that our proposed scheme satisfies the required QoS of handoff calls and keep the dropping probability of handoff calls lower than other schemes.

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Clock Routing Synthesis for Nanometer IC Design

  • Jin, Xianzhe;Ryoo, Kwang-Ki
    • Journal of information and communication convergence engineering
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    • v.6 no.4
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    • pp.383-390
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    • 2008
  • Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

A Study on the 3D-Puzzle Security Policy in Integrated Security System Network (통합보안 시스템 망 내 3차원-Puzzle 보안정책에 관한 연구)

  • Seo, Woo-Seok;Jun, Moon-Seog
    • The Journal of the Korea institute of electronic communication sciences
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    • v.5 no.4
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    • pp.425-434
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    • 2010
  • This study shows a limit to attacks that the prevention system, which is used as the mutual third aggressive packet path between open heterogeneous networks and applies prevention techniques according to the trace like IP tracking and attack methods, can prevent. Therefore, the study aims to learn information of constant attack routing protocol and of the path in network, the target of attack and build a database by encapsulating networks information routing protocol operates in order to prevent source attack paths. In addition, the study is conducted to divide network routing protocols developed from the process of dividing the various attack characters and prevent various attacks. This study is meaningful in that it analyzes attack path network and attacks of each routing protocol and secure exact mechanism for prevention by means of 3D-Puzzle, Path, and Cube of the integrated security system which is an implementation method of integrated information protection for access network defense.

The Layout Design of Structured Building Block Integrated Circuit (조립된 Building Block IC의 설계디자인의 문제)

  • Yi, Cheon-Hee
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.24 no.6
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    • pp.1056-1067
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    • 1987
  • This paper presents a design procedure for building block integrated circuits that is based on the digraph relaxation model. A set of optimization procedure is prosented for a minimum area and routing-fecsible placement of IC building blocks. Chip area optimization is subject to perimeter and area constraints on the component rectangles in the dissection.

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