• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.62-64
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• 2018

In two-stage single-phase inverters, inherent double line frequency component is present at both input and output of the front-end converter. Generally large electrolytic capacitors are required to eliminate the ripple. It is well known that the low frequency ripple shortens the lifespan of the capacitor hence the system reliability. However, the ripple can hardly be eliminated without the hardware combined with an energy storage device or a certain control algorithm. In this paper, a novel power-decoupling control method is proposed to eliminate the double line frequency ripple at the front-end converter of the DC/AC power conversion system. The proposed control algorithm is composed of two loop, ripple rejection loop and average voltage control loop and no extra hardware is required. In addition, it does not require any information from the phase-locked-loop (PLL) of the inverter and hence it is independent of the inverter control. In order to prove the validity and feasibility of the proposed algorithm a 5kW Dual Active Bridge DC/DC converter and a single-phase inverter are implemented, and experimental results are presented.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.140-142
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• 2007

This paper presents an effective method of precise velocity control at low speed with a low resolution encoder. Multirate observer to estimate the velocity at every DSP control period is used except a constant velocity mode. The observer corrects the estimation error when detects pulse signal. Unlike the conventional methods, the multirate estimator is stable at a low speed. However, the multirate estimator shows ripples at a constant velocity. Thus, in this paper we use a velocity prediction method which uses the present velocity from the previous average velocity to reject the ripple. In a summary, at a constant speed mode, the predicted velocity is used. Otherwise, the estimated velocity by the multirate obvserver is used. The effectiveness of the multirate observer and ripple rejection at low speed is verified through various simulations.

• Journal of IKEEE
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• v.21 no.3
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• pp.264-267
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• 2017

In this paper, A low dropout (LDO) regulator that improves the power supply rejection ratio by using a noise canceling circuit is proposed. The noise rejection circuit between the error amplifier and the pass transistor is designed to reduce the influence of the pass transistor on the noise coming from the voltage source. The LDO regulator has the same regulation characteristics as the conventional LDO regulator. The proposed circuit uses 0.18um process and Cadence's Virtuoso and Specter simulator.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.83-87
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• 2015

This paper presents a simple notch filter, which is so suitable for three-phase unbalanced and distorted power line. In the d-q synchronous transformation, three-phase unbalanced and distorted voltages generate lots of ripple voltages on d-q axes. The ripples make disturbances on controllers such as PLL of phase tracking. Unbalanced state makes ripple of double the frequency of power line. Odd harmonics 5th and 7th on the line make even 4th and 6th ripples on d-q axes due to the rotating reference frame, respectively. Cascaded two comb filters, delay lines 1/4T and 1/8T, are adopted for the ripple rejection. The filter rejects harmonics 2nd, 4th, 6th, 10th and so on. They are very effective to remove the ripples of both unbalance and distortion. The filter, implemented by two FIFOs on an experimental system, is adopted on a PLL controller of power line phase tracking. Through the simulation and experimental results, performance of the proposed comb filter has been validated.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• The Journal of the Acoustical Society of Korea
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• v.18 no.4
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• pp.23-30
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• 1999

In this study, we propose a new optimization algorithm for a withdrawal weighted SAW transversal filter to satisfy given, specifications such as bandwidth, ripple, insertion loss, and sidelobe rejection level. An analysis tool for the withdrawal weighted filter has been produced by means of the delta function model, and has been applied to the design of a filter consisting of an uniform input IDT and a withdrawal weighted output IDT. This optimization algorithm consists of three routines, which eventually determines eight design parameters to satisfy the performance specifications. At the first step, the number of input and output IDT fingers and their geometrical size are determined by the insertion loss specification. At the next step, the bandwidth is controlled by the change of the IDT finger position. Finally, the sidelobe rejection level is modified through the add/skip technique of IDT fingers. The algorithm in this paper is distinct from conventional techniques in that it can simultaneously consider all the specifications such as bandwidth, ripple, sidelobe rejection level and insertion loss, and optimize the geometry of the withdrawal weighted SAW filter.

• Journal of Power Electronics
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• v.19 no.4
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• pp.881-893
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• 2019

This paper proposes a practical sliding-mode controller design for shaping the impedances of cascaded boost-converter power decoupling circuits for reducing the second order harmonic ripple in photovoltaic (PV) current. The cascaded double-boost converter, when used as power decoupling circuit, has some advantages in terms of a high step-up voltage-ratio, a small number of switches and a better efficiency when compared to conventional topologies. From these features, it can be seen that this topology is suitable for residential (PV) rooftop systems. However, a robust controller design capable of rejecting double frequency inverter ripple from passing to the (PV) source is a challenge. The design constraints are related to the principle of the impedance-shaping technique to maximize the output impedance of the input-side boost converter, to block the double frequency PV current ripple component, and to prevent it from passing to the source without degrading the system dynamic responses. The design has a small recovery time in the presence of transients with a low overshoot or undershoot. Moreover, the proposed controller ensures that the ripple component swings freely within a voltage-gap between the (PV) and the DC-link voltages by the small capacitance of the auxiliary DC-link for electrolytic-capacitor elimination. The second boost controls the main DC-link voltage tightly within a satisfactory ripple range. The inverter controller performs maximum power point tracking (MPPT) for the input voltage source using ripple correlation control (RCC). The robustness of the proposed control was verified by varying system parameters under different load conditions. Finally, the proposed controller was verified by simulation and experimental results.

• Journal of electromagnetic engineering and science
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• v.6 no.2
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• pp.110-116
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• 2006

A reflective array type surface acoustic wave(SAW) dispersive delay line(DDL) with high time-bandwidth at the V/UHF-band is designed and fabricated for compressive receiver applications. This type of the SAW DDL has the properties of the relative bandwidth of 20 %, the time delay of 49.89 usec, the insertion loss of 38.5 dB and the side lobe rejection of 39 dB. In comparison with a commercial SAW DDL, the insertion loss, amplitude ripple and side lobe rejection are improved by $1.5dB{\pm}0.6dB$ and 4 dB respectively. Using the fabricated SAW DDL, the prototype of the compressive receiver is developed. It is composed of RF converter, fast tunable LO, chirp LO, A/D converter, signal processing unit and control unit. This prototype system shows a fine frequency resolution of below 30 kHz with high scan rate.

• Journal of Korea Society of Industrial Information Systems
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• v.24 no.6
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• pp.35-42
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• 2019

In this paper, we analyze the practical problems of the regenerative start method proposed to improve the starting characteristics of the TBM(Tunnel boring machine)system and propose a solution. In order to solve the speed ripple problem in the previous research results, we first analyze the problems occurring in the system and propose a method to compensate for them. By applying the improved method to the actual system, we compared the results with the conventional system and verified the effect of the proposed method.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.207-209
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• 2019

This paper proposes a grid-tied photovoltaic (PV) system, consisting of Voltage-fed dual-active-bridge (DAB) dc-dc converter with single phase inverter. The proposed converter allows a small dc-link capacitor, so that system reliability can be improved by replacing electrolytic capacitors with film capacitors. The double line frequency free maximum power point tracking (MPPT) is also realized in the proposed converter by using Ripple Correlation method. First of all, to eliminate the double line frequency ripple which influence the reduction of DC source capacitance, control is developed. Then, a designing of Current control in DQ frame is analyzed and to fulfill the international harmonics standards such as IEEE 519 and P1547, $3^{rd}$ harmonic in the grid is directly compensated by the feedforward terms generated by the PR controller with the grid current in stationary frame to achieve desire Total Harmonic Distortion (THD). 5-kW PV converter and inverter module with a small dc-link film capacitor was built in the laboratory with the proposed control and MPPT algorithm. Experimental results are given to validate the converter performance.