• 전자공학회논문지B
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• 제33B권12호
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• pp.24-30
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• 1996

In this paper, we designed a new type of high frequency on-chip voltage controlled oscillator (VCO) using GaAs MESFET, and their performances were comapred with those of the conventional VCO. Each VCO was designed with three-to-five ring oscillator and inverter, buffer and NOR gate were implemented by GaAs source coupled FET logic, which has better speed and noise performance compared to other GaAs MESFET logic. SPICE simulation showed that the gain of conventional and our new VCO was 1.24[GHz/V], 0.54[GHz/V], respectively. The frquency tuning range were 2.31 to 3.55 [GHz] for conventional VCO and 2.47 to 3.01[GHz] for our new design. This shows that the factor of two gain reductin was achieved without too much sacrifice in the oscillation frequency. For our new VCO, the average temperature index was -2[MHz/.deg. C] in the range of -20~85[.deg. C] the power supply noise index was 5[MHz/%] for 5.3[V].+-.10[%] and total power consumption was 60.58[mW].

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.194-201
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• 2015

A frequency modulated ultra-wideband (FM-UWB) transmitter with a high-robust relaxation oscillator for subcarrier generation and a dual-path Ring VCO for RF FM is proposed, featuring low power and low complexity. A prototype 3.65-4.25 GHz FM-UWB transceiver employing the presented transmitter is fabricated in $0.18{\mu}m$ CMOS for short-range wireless data transmission. Experimental results show a bit error rate (BER) of $10^{-6}$ at a data rate of 12.5 kb/s with a communication distance of 60 cm is achieved and the power dissipation of 4.3 mW for the proposed transmitter is observed from a 1.8 V supply.

• 전기학회논문지
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• 제60권2호
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• pp.451-454
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• 2011

In this paper, a wideband clock generator using novel Automatic frequency calibration(AFC) scheme is proposed. Wideband clock generator using AFC has the advantage of small VCO gain and wide frequency band. The conventional AFC compares whether the feedback frequency is faster or slower then the reference frequency. However, the proposed AFC can detect frequency difference between reference frequency with feedback frequency. So it can be reduced an operation time than conventional methods AFC. Conventional AFC goes to the initial code if the frequency step changed. This AFC, on the other hand, can a prior state code so it can approach a fast operation. In simulation results, the proposed clock generator is designed for DisplayPort using the CMOS ring-VCO. The VCO tuning range is 350MHz, and a VCO frequency is 270MHz. The lock time of clock generator is less then 3us at input reference frequency, 67.5MHz. The phase noise is -109dBC/Hz at 1MHz offset from the center frequency. and power consumption is 10.1mW at 1.8V supply and layout area is $0.384mm^2$.

• 한국정보통신학회논문지
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• 제17권7호
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• pp.1538-1543
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• 2013

평면형 마이크로스트립 공진기를 이용한 고주파 발진기의 단점인 위상잡음 특성을 개선하기 위해 본 논문에서는 분리형 링 공진기를 제안하였다. 제안된 공진기를 이용하여 위상잡음 특성 개선 효과를 나타내기 위해 발진기를 설계하여, 5.8GHz 기본 주파수에서 7.22dBm의 출력과 -83.5 dBc@100kHz의 위상잡음 특성을 나타내었다. 이것은 ${\lambda}/4$ 마이크로스트립 공진기를 이용한 발진기와 비교하여 위상잡음 특성이 9.7dB 정도 개선되었다. 다음은 제안된 공진기에 버랙터다이오드를 추가하여 전압제어발진기를 구현하였다. 발진기의 특성은 최소 5.833 GHz에서 최대 5.845 GHz 까지 125 MHz 정도의 튜닝범위를 가지고, -118~-115.5 dBc/Hz@100 KHz의 위상잡음 특성을 갖는다. 본 논문의 발진기는 평면형 구조로 쉬운 작업공정과 소형화 특성 때문에 MIC 또는 MMIC 분야의 설계에 응용될 수 있을 것이다.

• 센서학회지
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• 제28권2호
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.519-520
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• 2006

In this paper, we propose a voltage-controlled ring oscillator (VCO) for a 900 MHz low-noise fractional-N frequency synthesizer. The VCO delay cell is based on an nMOS source-coupled pair with load elements [1] and a combined tail current sources which consist of a large and a small current source to control the integer and fractional behaviors, respectively. The Spectre simulation results of the scheme in a 0.18um CMOS process show the accurate control of the KVCO better than the conventional one.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.267-269
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• 2007

PLL(Phase Locked Loop) are widely used circuit technique in modern electronic systems. In this paper, We propose the low voltage and high speed PLL. We design the PFD(Phase Frequency Detector) by using TSPC (True Single Phase Clock) circuit to improve the performance and solve the dead-zone problem. We use CP(Charge Pump} and LP(Loop filter) for Negative feedback and current reusing in order to solve current mismatch and switch mismatch problem. The VCO(Voltage controlled Oscillator) with 5-stage differential ring oscillator is used to exact output frequency. The divider is implemented by using D-type flip flops asynchronous dividing. The frequency divider has a constant division ratio 32. The frequency range of VCO has from 200MHz to 1.1GHz and have 1.7GHz/v of voltage gain. The proposed PLL is designed by using 0.18um CMOS processor with 1.8V supply voltage. Oscillator's input frequency is 25MHz, VCO output frequency is 800MHz and lock time is 5us. It is evaluated by using cadence spectra RF tools.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.340-343
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• 1999

In this paper, we propose a wide range PLL(Phase Locked Loop) for 64X CD-ROMs & l0X DVD-ROMs. The frequency locking range of the Proposed PLL is 75MHz~370MHz. To reduce jitters caused by large VCO gain and supply voltage noise, a new V-I converter and a differential delay cell are used in 3-stage ring VCO, respectively. The new V-I converter has a 0.6V ~ 2.5V wide input range. In addition, we propose a new charge pump which has perfect current matching characteristics for the sourcing/sinking current. This new charge pump improves the locking time and the locking range of the PLL. This Chip is implemented in 0.25${\mu}{\textrm}{m}$ CMOS process. It consumes 55㎽ in worst case with a single 2.5V power supply.