• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.3
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• pp.32-39
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• 2009

In this paper, system optimization design technique of an impulse ground penetrating image radar (GPIR) in time domain is proposed to improve depth resolution of the system. For the purpose, time domain analysis method of key components such as impulse generator and UWB antenna is explained and by simulation, parameters of each component are determined. In particular, by standardizing the impulse signal, spectrum efficiency of a radiated impulse signal is improved and a U-shaped planar dipole antenna for a UWB antenna is developed. By equipping a parabolic metal reflector with the proposed antenna, external noise is prevented and the ability of radiating an input impulse into ground is improved. In addition, to remove ringing effect of the propose antenna which causes serious degradation of the system performance, resistors are loaded at the edge of the antenna and then Tx and Rx UWB antennas are optimized by simulation in time domain. For images of targets buried under the ground migration technique is applied and influence of tough ground surface on distortion of received impulse signals is reduced using technique of noise and signal distortion reduction in time domain and its time resolution is enhanced. To verify the design optimization procedure, a prototype of an GPIR and an artificial test field are made. Measurement results show that the resolution of the system designed is as good as that of a theoretical model.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.12
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• pp.933-940
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• 2017

A wireless power transfer system with a negative impedance converter(NIC) was designed and tested. The system was investigated to identify the effects of ferrites and conductors. To improve the power transfer efficiency(PTE), the Q-factor of the transmitter was enhanced by the negative resistance generated by the NIC. The NIC was composed of an Op-Amp and resistors. The negative resistance was obtained with respect to a resistor connected in a feedback loop. The dimension of the Tx coil was $250mm{\times}250mm{\times}0.8mm$. The impedance and Q-factor were $31+j1874{\Omega}$ and 60, respectively. The negative resistance was selected to be $30{\Omega}$, and the Q-factor was increased to 900 by reduction of the transmitter resistance, which was about 15 times higher than that of a conventional transmitter. The measured PTE was greatly improved in comparison to that of a conventional system. These results demonstrate that the PTE is enhanced by using the NIC.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.897-903
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• 2011

This paper presents a highly linear power amplifier MMIC, having an output power level of about 1 watt, based on InGaP/GaAs hetero-junction bipolar transistor(HBT) technology for the 900 MHz band. The active bias circuit is applied to minimize the effect of temperature variation. Ballast resistors are optimized to prevent a current collapse and a thermal runaway. The fabricated power amplifier exhibited a gain of 17.6 dB, an output P1dB of 30 dBm, and a PAE of 44.9 % at an output P1dB from the one-tone excitation. It also showed a very high OIP3 of 47.3 dBm at an average output power of 20 dBm from the two-tone excitation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.1-8
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• 2006

In this paper, we suggested a new antenna structure for the RFID(Radio Frequency IDentification) reader. The conventional RFID reader uses a loop antenna. The central area of a loop antenna shows a low magnetic field strength, especially for the case of a large loop antenna diameter. We proposed a parallel-fed multiple loop antenna. Simulation and measurement were carried out for a single loop antenna, series-fed and parallel-fed multiple loop antennas. Simulation results show that we can obtain 0.40A/m, 0.68A/m, 1.98A/m of magnetic field strengths at the central point of a reader antenna for a single loop antenna, series-fed and parallel-fed multiple loop antennas, respectively. We measured the $79mm{\time}48mm$ tag area averaged induced voltages with applying 20Vp-p same source signals to reader antennas through the resistors. Measured tag area averaged induced voltages at the central point of a reader antennas were 0.76V, 1.45V, 4.04V for a single loop antenna series-fed and parallel-fed multiple loop antennas, respectively. The results show that we can get high induced voltage which can grantee a longer reading distance with a proposed parallel-fed multiple loop antenna.

• Journal of the Korean Society for Railway
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• v.12 no.4
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• pp.582-589
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• 2009

The energy generated by braking vehicle would simply be converted into waste heat by its braking resistors if no other vehicle is accelerating at exactly the same time. Up to 45% of the tractive power of vehicles capable of returning energy to the power supply can be regenerated during braking and that this energy can be used to feed vehicles which are accelerating at the same time. Such synchronized braking and accelerating can not be coordinated, the ESS(energy storage system, here after) stores the energy generated during braking and discharges it again when a vehicle accelerates. The ESS is able to store and discharge energy extremely quickly, consequently enabling a complete exchange of energy between vehicles, even if they are not braking and accelerating at precisely the same time, as is most frequently the case in everyday service. The energy saving rate is related to the headway. If the headway is long/short, the energy saving goes up/down, When the headway is short, the ESS can not save much regenerative energy. The headway of SeoulMetro line 2 as the worst case is very short in Korea urban transit system. So, the energy saving rate will be very low. If the ESSs are applied to another railway system, we can expect that the effectiveness is better than the results of SeoulMetro line 2. This paper presents effects of energy saving obtained by applying the ESS to SeoulMetro line 2.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.61-70
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• 2016

This paper describes a new PMU(parametric measurement unit) design technique for automatic test equipment(ATE). Only one DDA(differential difference amplifier) is used to force the test signals to DUT(device under test), while conventional design uses two or more amplifiers to force test signals. Since the proposed technique does not need extra amplifiers in feedback path, the proposed PMU inherently guarantees stable operation. Moreover, to measure the response signals from DUT, proposed technique also adopted only one DDA amplifier as an IA(instrument amplifier), while conventional IA uses 3 amplifiers and several resistors. The DDA adopted two rail-to-rail differential input stages to handle full-range differential signals. Gain enhancement technique is used in folded-cascode type DDA to get open loop gain of 100 dB. Proposed PMU design enables accurate and stable operation with smaller hardware and lower power consumption. This PMU is implemented with 0.18 um CMOS process and supply voltage is 1.8 V. Input ranges for each force mode are 0.25~1.55 V at voltage force and 0.9~0.935 V at current force mode.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.47-53
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• 2012

Bonding strength of Sn-3.0Ag-0.5Cu solder joint due to degradation characteristic of OSP surface finish was investigated, compared with SnPb finish. The thickness variation and degradation mechanism of organic solderability preservative(OSP) coating were also analyzed with the number of reflow process. To analyze the degradation degree of solder joint strength, FR-4 PCB coated with OSP and SnPb were experienced preheat treatment as a function of reflow number from 1st to 6th pass, respectively. After 2012 chip resistors were soldered with Sn-3.0Ag-0.5Cu on the pre-heated PCB, the shear strength of solder joints was measured. The thickness of OSP increased with increase of the number of reflow pass by thermal degradation during the reflow process. It was also observed that the preservation effect of OSP decreased due to OSP degradation which led Cu pad oxidation. The mean shear strength of solder joints formed on the Cu pads finished with OSP and SnPb were 58.1 N and 62.2 N, respectively, through the pre-heating of 6 times. Although OSP was degraded with reflow process, the feasibility of its application was proven.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.4
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• pp.1-7
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• 1999

We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

• Journal of the Society of Disaster Information
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• v.13 no.3
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• pp.305-312
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• 2017

In our society, the advanced, advanced, and information industries have continued to grow and now live in the era of the fourth industrial revolution. As the industry develops, the load of the users has also increased so much that it is deepened by the energy shortage phenomenon and the construction of additional energy facilities is required. Therefore, energy plant construction work is being actively carried out in the coastal area. In particular, it is common to build a plant in the ground by filling the coast with soil in other regions, reflecting the fact that Korea is lacking in the country when constructing power plants, gas and petrochemical plants. Current domestic grounding designs are designed or constructed to suit only the use of grounding resistors based on the electrical equipment design technical standards. However, in the case of a plant facility constructed in the untested buried soil, when the lightning current and the abnormal current are inputted, the facility operator or the user due to the elevation of the ground potential is seriously exposed to the risk of electric shock disaster. In this paper, we analyze the ground resistivity of the landfilled soil and use a computer program (CDEGS) based on KS C IEC 61936-1, We analyze the contact voltage and stratification voltage and propose a grounding design optimized for plant installation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.