• Journal of the Korean institute of surface engineering
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• v.49 no.5
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• pp.408-415
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• 2016

The offshore structures exposed to harsh corrosive such as the marine environment is essential for the quality management technique throughout the life cycle of initial design, construction and operation. Also, it should satisfy the design life and ensure the safety of the substructure with optimization of design process. This study focused on optimization of design condition for corrosion protection of wind turbine structure and computational analyzing was performed to evaluate the performance of corrosion protection with utilizing practical experimental data. We expect this analytical study contribute to improve the corrosion maintenance stability and economical efficiency of designing wind turbine structures. As a result, the design of cathodic protection system using sacrificial anodes required accurate identification of current density in order to meet the long term design life, which can be seen that a change of structure surface's coating breakdown factor is one of the key influencing factors.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.107-116
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• 2001

A multithreaded model is a hybrid one which combines locality of execution of the von Neumann model with asynchronous data availability and implicit parallelism of the dataflow model. Much researches that have been made toward the advanced performance of multithreaded models are about the cache memory which have been proved to be efficient in the von Neumann model. To use an instruction cache or operand cache, the multithreaded models must have cache memories. If cache memories are added to the multithreaded model, they may have the disadvantage of high implementation cost in the mode. To solve these problems, we did not add cache memory but applied the method of executing the caching by using available registers of the multithreaded models. The available register-based caching method is one that use the registers which are not used on the execution of threads. It may accomplish the same effect as the cache memory. The multithreaded models can compute the number of available registers to be used during the process of the register optimization, and therefore this method can be easily applied on the models. By applying this method, we can also remove the access conflict and the bottleneck of frame memories. When we applied the proposed available register-based caching method, we found that there was an improved performance of the multithreaded model. Also, when the available-register-based caching method is compared with the cache based caching method, we found that there was the almost same execution overhead.

• Journal of the Korea Computer Industry Society
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• v.5 no.9
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• pp.1079-1088
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• 2004

Generally, the code motion algorithm accomplishes the run-time optimal connected with the computational optimifation and the register overhead This paper proposes a sparse code motion, which considers the code size, in addition to computational optimization and lifetime optimization. The BCM algorithm carries out the optimal code motion computationally and the LCM algorithm reduces the register overhead in a sparse code motion algorithm. A sparse code motion algorithm is optimum algorithm computationally and lifetime because of suppression unnecessary code motion This algorithm improves runtime and efficiency of the program than the previous work through the performance test.

• Bulletin of the Society of Naval Architects of Korea
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• v.17 no.4
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• pp.46-54
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• 1980

The ship structural design problem is formulated as a general nonlinear optimization problem with constraints. Characteristics of the general structural problems and various optimization techniques are discussed, with special emphasis on penalty function method for constrained problems. A simple example of the solution of a midship structure design of cargo vessel, which complies with the rules of the Korean Register of Shipping is shown using SUMT-exterior method with some search methods.

• The Transactions of the Korea Information Processing Society
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• v.6 no.8
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• pp.2196-2203
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• 1999

This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

• Journal of the Society of Naval Architects of Korea
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• v.53 no.2
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• pp.108-114
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• 2016

Recently, there has been a growing interest in marine leisure sports and high speed power boat for fishing. The prototype of 20 feet class power boat was developed and authors are joined in this government-led project. The research was performed to evaluate the optimal structure and design of the structural strength necessary to ensure the structural safety of the power boat. A new material ROCICORE fiber added to the mat and roving was adopted for high-power tenacity. ANSYS Workbench has been used to make the structural model, evaluate the strength and optimize the structural design. The response of the structure to quasi-static slamming loads according to the rules and regulations of ISO 12215-5, Lloyd’s Register of Shipping and Korean Register has been implemented and studied. An optimization study for the structural response is carried out by changing the plate thickness and section modulus of stiffeners. The power boat structure derived fuel efficiency is optimized by performing the best possible structural design to minimize the hull weight.

• Journal of the Korea Society of Computer and Information
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• v.5 no.3
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• pp.1-8
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• 2000

Prepass code scheduling(code scheduling before register allocation), the register lifetimes may be lengthened, which may increase the amount of data dependence relations. So, it makes difficult to allocate the registers because of complex interference graph. In this paper, to improve that defect, propose an 2-phase coloring method. At first phase-1 assign the registers to variables which have long live ranges. Secondly, phase-2 allocate the registers to remained variables to minimize the register allocation cost. Experimental results shown that proposed method is more efficient scheme than Chaitin's scheme when prepass code scheduling.

• Journal of Ocean Engineering and Technology
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• v.28 no.4
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• pp.294-305
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• 2014

In offshore structures, fire is one of the most important hazardous events. The concern of fires has recently been reflected in the rules and quantified risk assessment based design practice. Within the framework of quantified risk assessment and the management of offshore installations, therefore, more refined computations of the consequences or hazardous action effects due to fire are required. To mitigate fire risk, passive fire protection(PFP) is widely used on offshore structures. This study presents methods for a nonlinear structural response analysis considering the PFP effects under fires. It is found that a structural response analysis is most likely to use valuable technology for the optimization and design of offshore structures with PFP. Thermal and structural response analyses have been performed using LS-DYNA and FAHTS/USFOS. The results of these structural response analyses are compared with each other.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.47-55
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• 2010

In this paper, a timing register architecture using demultiplexer and counter is proposed to reduce the area of the high resolution SAR type analog to digital converter. The area and digital power consumption of the conventional timing register based on the shift register is drastically increased, as the resolution is increased. On the other hand, the proposed architecture results in reduction of the area and the power consumption of the error correction logic of the SAR ADC. This chip is implemented with 0.18 um CMOS process. The area is reduced by 5.4 times and the digital power consumption is minimized compared with the conventional one. The 12 bits SAR ADC shows ENOB of 11 bits, power consumption of 2 mW, and conversion speed of 1 MSPS. The die area is $1 mm{\times}1mm$.

• Structural Engineering and Mechanics
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• v.59 no.6
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• pp.993-1017
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• 2016

Helicopters are essential for supporting offshore oil and gas activities around the world. To ensure accessibility for helicopters, helideck structures must satisfy the safety requirements associated with various environmental and accidental loads. Recently, offshore helideck structures have used aluminium because of its light weight, low maintenance requirements, cost effectiveness and easy installation. However, section designs of aluminum pancakes tend to modify and/or change from the steel pancakes. Therefore, it is necessary to optimize section design and evaluate the safety requirements for aluminium helideck. In this study, a design procedure was developed based on section optimization techniques with experimental studies, industrial regulations and nonlinear finite element analyses. To validate and verify the procedure, a new aluminium section was developed and compared strength capacity with the existing helideck section profiles.