• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.194-198
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• 2003

A 16-bit adiabatic low-power Micro-processor core is designed. The processor consists of control block, multi-port register file and ALU. A simplified four-phase clock generator is designed to provide supply clocks for adiabatic processor. All the clock line charge on the capacitive interconnections is recovered to recycle the energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and $0.35\mu\textrm$ CMOS technology is used. Simulation results show that the power consumption of the adiabatic Microprocessor core is reduced by a factor of 2.9~3.1 compared to that of conventional CMOS Microprocessor

• Information and Communications Magazine
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• v.25 no.12
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• pp.10-18
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• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.12 no.2
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• pp.141-146
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• 1994

At the present time the cadastral sections has a document for constructing database of land register and commit to record the assessed cost of land in field. Kumjung-Ku, Pusan is a model in this study. It is possible to investigate the present land record by connecting graphic data with attribute data in author's program. AutoCAD make possible to connect graphic data with attribute data. Because of limitation of constructing database in AutoCAD, authors construct independent database in Clipper's circumstance. Database in AutoCAD and Clipper is connected to the menu-file in AutoCAD's circumstance.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1563-1566
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• 2002

A 16-bit adiabatic datapath for micro-power RISC processor is designed. The datapath is composed of a 3-read and 1-write multi-port adiabatic register file and an arithmetic and logic unit. A four-phase clock generator is also designed to provide supply clocks fer adiabatic circuits and the driving capability control scheme is proposed. All the clock line charge on the capacitive interconnections is recovered to recycle energy. Adiabatic circuits are designed based on efficient charge recovery logic(ECRL) and are implemented using a 0.35 fm CMOS technology. Functional and energy simulation is carried out to show the feasibility of adiabatic datapath. Simulation results show that the power consumption of the adiabatic datapath including supply clock generator is reduced by a factor of 1.4∼1.5 compared to that of the conventional CMOS.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.781-783
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• 2005

ARM 프로세서는 내장형 시스템에서 가장 널리 사용되는 32비트 마이크로 프로세서 중 하나이며, Thumb 명령어 세트는 보다 작은 코드 크기를 위해 제공하는 16비트 확장 명령어 세트이다. Thumb의 약점중의 하나는 줄어든 명령어 길이 때문에 이용할 수 있는 레지스터의 개수가 반으로 줄어든다는 것인데 결과적으로 가용 레지스터의 부족으로 인해 spill 코드가 빈번하게 발생할 수 있다. 우리는 약간의 하드웨어 및 명령어 수정을 통해 뱅크(bank)로 이루어진 레지스터 파일을 제공하고자 한다. 이로 인해 컴파일러는 보다 여유 있는 레지스터를 확보하게 되어 spill 코드가 줄어들게 되므로 보다 작은 크기의 코드를 얻어낼 수 있다. 이 변화된 형태의 레지스터 파일을 운용하기 위한 효율적인 레지스터 할당기법이 요구되며, 제안하는 영역기반 레지스터 할당기법을 통해 이이 최적화된 Thumb 코드 대비 약 $5.1\%$의 코드 크기 감소효과를 볼 수 있었다.

• International Journal of Contents
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• v.9 no.2
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• pp.22-26
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• 2013

Comparing online and paper-based environment for report submission and correction, the former supersedes to the latter, since (1) the turn-around time becomes shorter, (2) teaching opportunity increases, and (3) as a consequence, the student's achievement level becomes higher in the online environment. In this paper, we propose an annotation tool GABA for PDF document in order to reduce correction time by the teachers and to facilitate instruction to students. In a usual class, the same or similar assignments are given to the students. Then it is often the case that many students make similar mistakes. A teacher can register and classify common correction comments to GABA. Report correction time becomes significantly shorter by reusing the registered comments. GABA also provides various support functions in order to assist efficient checking of numerous report files such as (1) sorting of frequently-used comments, (2) similarity-based file sorting, and (3) cross tabulation of comments using category and weight.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.29-35
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• 1998

This paper describes architectures and design of a SIMD type parallel image processing chip called SliM-II. The chiphas a linear array of 64 processing elements (PEs), operates at 30 MHz in the worst case simulation and gives at least 1.92 GIPS. In contrast to existing array processors, such as IMAP, MGAP-2, VIP, etc., each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU operation, data I/O, and inter-PE communication simulataneously in a single instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel move between the register file and on-chip memory as in DSP chips, SliM-II can greatly reduce the inter-PE communication overhead, due to the idea a sliding, which is a technique of overlapping inter-PE communication with computation. Moreover, the bandwidth of data I/O and inter-PE communication increases due to bit-parallel data paths. We used the COMPASS$^{TM}$ 3.3 V 0.6.$\mu$m standrd cell library (v8r4.10). The total number of transistors is about 1.5 muillions, the core size is 13.2 * 13.0 mm$^{2}$ and the package type is 208 pin PQ2 (Power Quad 2). The performance evaluation shows that, compared to a existing array processors, a proposed architeture gives a significant improvement for algorithms requiring multiplications.s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5B
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• pp.286-294
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• 2007

In ASIP design, compiler is required for performance evaluation of processors being designed. The design of machine specific compiler is time consuming. This paper presents the system which generates C compiler from MDL descriptions. Compiler generation using MDL can support user retargetability and concurrency between compiler design and processor design. However, it must overcome semantics gap between compiler and machine. To handle this problem, the proposed system maps behavioral descriptions to library which contains abstract behavior for each tree pattern. Using mapped instructions and information on register file usage, the proposed system generates back-end interface function of the compiler. Generated compilers, for MIPS R3000, ARM9 cores, have been proved by application programs written in C code.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.31-38
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• 2003

A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.