1 |
R. Leupers and P. Marwedel, 'Retargetable Generation of Code Selectiors from HDL Processor Models', in Proc. European Design & Test Conf., 1997
|
2 |
J. Ceng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun, 'C Compiler Retargeting Based on Instruction Semantics Models', in Proc. Design Automation and Test in Europe, pp. 1150-1155, 2005
|
3 |
H. Emmelmann, F.-W. Schro¨er, and R. Landwehr, 'Beg - A Generator for Efficient Back Ends', in Proc. SIGPLAN Conf. Programming Language Design and Implementation, pp 227-237, 1989
|
4 |
S. Furber, ARM System-on-chip Architecture, Addison-Wesley, 2000
|
5 |
D. Lanneer et al, 'CHESS : Retargetable Code Generation for Embedded DSP Processors', in P. Marwedel and G. Goosens, ed., Code Generation for Embedded Processors, pp. 85-102, Kluwer Academic Publishers, 1995
|
6 |
R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and F. Zadeck, 'Efficiently computing static single assignment form and the control dependence graph', ACM Trans. Program. Lang. Syst., Vol. 13, No. 4, pp. 451-490, Oct. 1991
DOI
|
7 |
A. Fauth, J. Van Praet, and M. Freericks, 'Describing Instructions Set Processors using nML', in Proc. European Design & Test Conf., Paris (France), pp. 503-507, Mar. 1995
|
8 |
C. Fraser and D. Hanson, A Retargetable C Compiler : Design and Implementation, Benjamin/Cummings, 1995
|
9 |
S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer, 'The MIMOLA Language Version 4.1', Technical report, University of Dortmund, 1994
|
10 |
C. Fraser and D. Hanson, 'The lcc 4.x Code-Generation Interface', Microsoft Research, 2003
|
11 |
A. Hoffmann et al, 'A Novel Methodology for the Design of Application-Specific Instruction Set Processors(ASIPs) Using a Machine Description Language', IEEE Trans. Computer-Aided Design, Vol. 20, No. 11, pp. 1338-1354, Nov. 2001
DOI
ScienceOn
|
12 |
ACE - Associated Compiler Experts, The COSY Compiler Development System, http://www.ace.nl
|
13 |
M. Jain, M. Balakrishnan, and A. Kumar, 'ASIP Design Methodologies : Survey and Issues', in Proc. IEEE/ACM Int. Conf. VLSI Design. (VLSI 2001), pp. 76-81, Jan. 2001
|
14 |
조재범, 유용호, 황선영, '임베디드 프로세서 코어 자동생성 시스템의 구축', 한국통신학회논문지, 30권 6A호, pp. 526-534, 2005년 6월
과학기술학회마을
|
15 |
J. Ceng, W. Sheng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun, 'Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting'. Int. Workshop on Systems, Architectures, Modeling, and Simulation (SAMOS), 2004
|
16 |
B. Alpern, M. Wegman, and F. Zadeck, 'Detecting Equality of Value in Programs', in Conf. Record of the 15th ACM Symposium on Principles of Program Languages, ACM, New York, pp. 1-11, January 1988
|
17 |
J. V. Praet, D. Lanneer, G. Goossens, W. Geurts, and H. De Man, 'A Graph Based Processor Model for Retargetable Code Generation', in Proc. European Design & Test Conf., 1996
|
18 |
G. Kane and J. Heinrich, MIPS RISC Architecture, Prentice Hall, 1992
|
19 |
R. Leupers, 'Compiler Design Issues for Embedded Processors', IEEE Design & Test of Computers, Vol. 19, No. 4, pp. 51-58, July-Aug. 2002
DOI
ScienceOn
|
20 |
C. Fraser, R. Henry, and T. Proebsting, 'BURG - Fast Optimal Instruction Selection and Tree Parsing', ACM SIGPLAN Notices, Vol. 27, No. 4, pp. 68-76, April 1992
|
21 |
W. Yang, S. Horwitz, and T. Reps, 'Detecting Program Components with Equivalent Behaviors', Tech. Rep. 840. Dept. of Computer Science, Univ. of Wisconsin at Madison, Madison, Apr. 1989
|