• Title/Summary/Keyword: redundant architecture

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An Overview of Content Poisoning in NDN: Attacks, Countermeasures, and Direction

  • Im, Hyeonseung;Kim, Dohyung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.14 no.7
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    • pp.2904-2918
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    • 2020
  • With a huge demand for replicated content on the Internet, a new networking paradigm called information-centric networking (ICN) has been introduced for efficient content dissemination. In ICN, named content is distributed over the network cache and it is accessed by name instead of a location identifier. These aspects allow users to retrieve content from any of the nodes having replicas, and consequently 1) network resources are more efficiently utilized by avoiding redundant transmission and 2) more scalable services are provided by distributing server loads. However, in-network caching in ICN brings about a new type of security issues, called content poisoning attacks, where fabricated content is located in the network cache and interferes with the normal behavior of the system. In this paper, we look into the problems of content poisoning in ICN and discuss security architectures against them. In particular, we reconsider the state-of-the-art schemes from the perspective of feasibility, and propose a practical security architecture.

Ensemble convolutional neural networks for automatic fusion recognition of multi-platform radar emitters

  • Zhou, Zhiwen;Huang, Gaoming;Wang, Xuebao
    • ETRI Journal
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    • v.41 no.6
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    • pp.750-759
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    • 2019
  • Presently, the extraction of hand-crafted features is still the dominant method in radar emitter recognition. To solve the complicated problems of selection and updation of empirical features, we present a novel automatic feature extraction structure based on deep learning. In particular, a convolutional neural network (CNN) is adopted to extract high-level abstract representations from the time-frequency images of emitter signals. Thus, the redundant process of designing discriminative features can be avoided. Furthermore, to address the performance degradation of a single platform, we propose the construction of an ensemble learning-based architecture for multi-platform fusion recognition. Experimental results indicate that the proposed algorithms are feasible and effective, and they outperform other typical feature extraction and fusion recognition methods in terms of accuracy. Moreover, the proposed structure could be extended to other prevalent ensemble learning alternatives.

Logic gate implementation of constant amplitude coded CS/CDMA transmitter (정포락선 부호화된 CS-CDMA 송신기의 논리 게이트를 이용한 구현)

  • 김성필;류형직;김명진;오종갑
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.281-284
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    • 2003
  • Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

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A fault detection and recovery mechanism for the fault-tolerance of a Mini-MAP system (Mini-MAP 시스템의 결함 허용성을 위한 결함 감지 및 복구 기법)

  • Mun, Hong-Ju;Kwon, Wook-Hyun
    • Journal of Institute of Control, Robotics and Systems
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    • v.4 no.2
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    • pp.264-272
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    • 1998
  • This paper proposes a fault detection and recovery mechanism for a fault-tolerant Mini-MAP system, and provides detailed techniques for its implementation. This paper considers the fault-tolerant Mini-MAP system which has dual layer structure from the LLC sublayer down to the physical layer to cope with the faults of those layers. For a good fault detection, a redundant and hierarchical fault supervision architecture is proposed and its implementation technique for a stable detection operation is provided. Information for the fault location is provided from data reported with a fault detection and obtained by an additional network diagnosis. The faults are recovered by the stand-by sparing method applied for a dual network composed of two equivalent networks. A network switch mechanism is proposed to achieve a reliable and stable network function. A fault-tolerant Mini-MAP system is implemented by applying the proposed fault detection and recovery mechanism.

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A Cache Privacy Protection Mechanism based on Dynamic Address Mapping in Named Data Networking

  • Zhu, Yi;Kang, Haohao;Huang, Ruhui
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.12
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    • pp.6123-6138
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    • 2018
  • Named data networking (NDN) is a new network architecture designed for next generation Internet. Router-side content caching is one of the key features in NDN, which can reduce redundant transmission, accelerate content distribution and alleviate congestion. However, several security problems are introduced as well. One important security risk is cache privacy leakage. By measuring the content retrieve time, adversary can infer its neighbor users' hobby for privacy content. Focusing on this problem, we propose a cache privacy protection mechanism (named as CPPM-DAM) to identify legitimate user and adversary using Bloom filter. An optimization for storage cost is further provided to make this mechanism more practical. The simulation results of ndnSIM show that CPPM-DAM can effectively protect cache privacy.

Delamination analysis of inhomogeneous viscoelastic beam of rectangular section subjected to torsion

  • Victor I. Rizov
    • Coupled systems mechanics
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    • v.12 no.1
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    • pp.69-81
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    • 2023
  • This paper considers a delamination analysis of a statically undetermined inhomogeneous beam structure of rectangular section with viscoelastic behavior under torsion. The beam is built in at its two ends. The beam has two longitudinal inhomogeneous layers with a delamination crack between them. A notch is made in the upper crack arm. The external torsion moment applied on the beam is a function of time. Under these conditions, the beam has one degree of indeterminacy. In order to derive the strain energy release rate, first, the static indeterminacy is resolved. Then the strain energy release rate is obtained by analyzing the balance of the energy with considering the viscoelastic behavior. The strain energy release rate is found also by analyzing the compliance of the beam for checkup. Solution of the strain energy release rate in a beam without a notch in the upper crack arm is derived too. In this case, the beam has two degrees of static indeterminacy (the torsion moment in the upper crack arm is treated as an additional internal redundant unknown). A parametric investigation of the strain energy release rate is carried-out.

The Design of A Fast Two′s Complement Adder with Redundant Binary Arithmetic (RB 연산을 이용한 고속 2의 보수 덧셈기의 설계)

  • Lee, Tae-Uk;Jo, Sang-Bok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.5
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    • pp.55-65
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    • 2000
  • In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

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Fast RSA Montgomery Multiplier and Its Hardware Architecture (고속 RSA 하드웨어 곱셈 연산과 하드웨어 구조)

  • Chang, Nam-Su;Lim, Dae-Sung;Ji, Sung-Yeon;Yoon, Suk-Bong;Kim, Chang-Han
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.17 no.1
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    • pp.11-20
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    • 2007
  • A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

An Efficient Multicast Architecture for IP-Based Mobile Core Networks (IP기반 모바일 코어 네트워크에서의 효율적인 멀티캐스트 아키텍처)

  • Kim Won-Tea;Kim Hyo-Eun;Park Yong-Jin
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.6 s.348
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    • pp.9-22
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    • 2006
  • When the legacy multicast routing protocols are adopted in If-based mobile core networks, there are some problems such as traffic injection from unnecessary sources, traffic overhead by group management and router performance degradation by large amount of multicast session information. In this paper, we propose a stateless multicast mechanism which has no need to maintain multicast information for session status and reduces redundant network overhead for maintaining multicast tree. In addition interworking with IGMPv3 gets rid of traffic from unnecessary sources which have no registration from receivers. The operations of essential components including a gateway node for interworking with the legacy Internet multicast network, a gateway node for transparency to radio access network and a intermediate node in mobile core networks, are definitely defined and the proposed communication architecture is completed. Finally we evaluate and approve the performance of the proposed architecture by means of well-designed network simulation.

Design and Analysis of Resource Management Architecture for Network Mobility (네트워크 이동성을 위한 자원 관리 구조의 설계와 분석)

  • 백은경;조호식;최양희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.29 no.7B
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    • pp.628-640
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    • 2004
  • The demand for next generation networks can be condensed into always-best-connected, ubiquitous, mobile, all-lP, and converged networks. IPv6 has been introduced for all-IP ubiquitous communications, and vehicles are coming to represent an important communication platform. In this paper. we propose various resource management schemes for in-vehicle mobile networks, which are adaptive to different hardware configurations. We focus on power and wireless bandwidth since they are critical resources for mobile communications. Based on the mobility characteristics of in-vehicle networks, we propose vehicle-aware power saving schemes. The main idea behind these power saving schemes is to adjust mobile router (MR) advertisement interval and binding lifetime. In addition, according to different wireless environments, we propose adaptive bandwidth management schemes using multihoming: best-connected MR selection based on location, and high-data-rate MR selection based on priority By mathematical analysis, it is shown that our schemes save power prominently for both the dormant nodes and active nodes. In addition, simulation results show that proposed multiple mobile router architecture outperforms previous simple redundant router architecture in preserving session and providing sufficient bandwidth.