• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.117-124
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• 2010

Appling centralized network management architecture SNMP(Simple Network Management Protocol) to wireless networks causes the network overhead, NAT(Network Address Translation) problem on AP, and performance degradation of mobile nodes. In this paper, we propose an integrated management scheme for wired and wireless networks using mobile agents in order to solve above problems. In our proposed scheme, SNMP is applied to manage wired networks and MAs of SNMP are implemented in APs or wireless nodes to manage wireless networks. In addition, we propose a method to reduce the redundant OID information within SNMP response messages. Through the analysis, we show that our proposal resolves the given problems and reduces the processing delay of the wireless nodes.

• BMB Reports
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• v.46 no.8
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• pp.416-421
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• 2013

Genome-wide association studies (GWAS) have become popular as an approach for the identification of large numbers of phenotype-associated variants. However, differences in genetic architecture and environmental factors mean that the effect of variants can vary across populations. Understanding population genetic diversity is valuable for the investigation of possible population specific and independent effects of variants. EvoSNP-DB aims to provide information regarding genetic diversity among East Asian populations, including Chinese, Japanese, and Korean. Non-redundant SNPs (1.6 million) were genotyped in 54 Korean trios (162 samples) and were compared with 4 million SNPs from HapMap phase II populations. EvoSNP-DB provides two user interfaces for data query and visualization, and integrates scores of genetic diversity (Fst and VarLD) at the level of SNPs, genes, and chromosome regions. EvoSNP-DB is a web-based application that allows users to navigate and visualize measurements of population genetic differences in an interactive manner, and is available online at [http://biomi.cdc.go.kr/EvoSNP/].

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.223-230
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• 2004

We suggest on this paper the LTSA-based Guide System for elementary mathematics, that is useful in managing of educational contents, avoiding redundant contents-development and improving reusability of contents. And it gives more satisfaction to the learner by making leaner choose his own courses. We considered the educational differences between learners, for the learning not to be a mechanical thing, by giving the educational course and method adequate to the learner By focusing on the educational differences between learners resulted from elementary educational adaption example implemented on the base of the international standard, we suggested a method for activating the coaching process in the system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.763-767
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• 2005

RAID were proposed to stored double data or used to parity logging methode for error recovery. We describe a technique for automating the execution of redundant disk array operation, including recovery from errors, independent of array architecture. RAID5 provide highly reliable cost effective secondary storage with high performance for read access and large write accessed. It discusses the two architectural techniques used in disk arrays, striping across multiple disks to improve performance and redundancy to improve reliability. In this paper we compare with performance and reliability in RAID5 real/write to file and stripe size. than suggest to algorithm.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Journal of Korea Spatial Information System Society
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• v.1 no.2 s.2
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• pp.33-46
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• 1999

In distributed computing platforms like CORBA, wrappers are used to integrate heterogeneous systems or databases. A spatial data provider is one of the wrappers because it provides clients with uniform access interfaces to diverse data sources. The individual implementation of spatial data providers for each of different data sources is not efficient because of redundant coding of the wrapper modules. This paper presents a new architecture of the spatial data provider which consists of two layered objects : independent wrapper components and dependent wrapper components. Independent wrapper components would be reused for implementing a new data provider for a new data source, which dependent wrapper components should be newly coded for every data source. This paper furthermore discussed the issues of implementing the representation of query results in the middleware. There are two methods of keeping query results in the middleware. One is to keep query results as non-CORBA objects and the other is to transform query results into CORBA objects. The evaluation of the above two methods shows that the cost of making CORBA objects is very expensive.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2004.11a
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• pp.371-374
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• 2004

Induction motors are a critical component of many industrial processes and are frequently integrated in commercially available equipment. Safety, reliability, efficiency, and performance are some of the major concerns of induction motor applications. Preventive maintenance of induction motors has been a topic great interest to industry because of their wide range application of industry. Since the use of mechanical sensors, such as vibration probes, strain gauges, and accelerometers is often impractical, the motor current signature analysis (MACA) techniques have gained murk popularity as diagnostic tool. Fault tolerant control (FTC) strives to make the system stable and retain acceptable performance under the system faults. All present FTC method can be classified into two groups. The first group is based on fault detection and diagnostics (FDD). The second group is independent of FDD and includes methods such as integrity control, reliable stabilization and simultaneous stabilization. This paper presents the fundamental FDD-based FTC methods, which are capable of on-line detection and diagnose of the induction motors. Therefore, our group has developed the embedded distributed fault tolerant and fault diagnosis system for industrial motor. This paper presents its architecture. These mechanisms are based on two 32-bit DSPs and each TMS320F2407 DSP module is checking stator current, voltage, temperatures, vibration and speed of the motor. The DSPs share information from each sensor or DSP through DPRAM with hardware implemented semaphore. And it communicates the motor status through field bus (CAN, RS485). From the designed system, we get primitive sensors data for the case of normal condition and two abnormal conditions of 3 phase induction motor control system is implemented. This paper is the first step to drive multi-motors with serial communication which can satisfy the real time operation using CAN protocol.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2006.06a
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• pp.351-355
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• 2006

RSA 암호 시스템은 IC카드, 모바일 및 WPKI, 전자화폐, SET, SSL 시스템 등에 많이 사용된다. RSA는 모듈러 지수승 연산을 통하여 수행되며, Montgomery 곱셈기를 사용하는 것이 효율적이라고 알려져 있다. Montgomery 곱셈기에서 임계 경로 지연 시간(Critical Path Delay)은 세 피연산자의 덧셈에 의존하고 캐리 전파를 효율적으로 처리하는 문제는 Montgomery 곱셈기의 효율성에 큰 영향을 미친다. 최근 캐리 전파를 제거하는 방법으로 캐리 저장 덧셈기(Carry Save Adder, CSA)를 사용하는 연구가 계속 되고 있다. McIvor외 세 명은 지수승 연산에 최적인 CSA 3단계로 구성된 Montgomery 곱셈기와 CSA 2단계로 구성된 Montgomery 곱셈기를 제안했다. 시간 복잡도 측면에서 후자는 전자에 비해 효율적이다. 본 논문에서는 후자보다 빠른 연산을 수행하기 위해 캐리 전파 제거 특성을 가진 이진 부호 자리(Signed-Digit, SD) 수 체계를 사용한다. 두 이진 SD 수의 덧셈을 수행하는 잉여 이진 덧셈기(Redundant Binary Adder, RBA)를 새로 제안하고 Montgomery 곱셈기에 적용한다. 기존의 RBA에서 사용하는 이진 SD 덧셈 규칙 대신 새로운 덧셈 규칙을 제안하고 삼성 STD130 $0.18{\mu}m$ 1.8V 표준 셀 라이브러리에서 지원하는 게이트들을 사용하여 설계하고 시뮬레이션 하였다. 그 결과 McIvor의 2 방법과 기존의 RBA보다 최소 12.46%의 속도 향상을 보였다.

• Journal of the Korea Institute of Military Science and Technology
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• v.23 no.6
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• pp.639-649
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• 2020

Air data systems measure airspeed, pressure altitude, angle of attack and angle of sideslip. These measurements are essential for operating flight control laws to ensure safe flights. Since the loss or corruption of air data measurements is considered as catastrophic, a high level of operational reliability needs to be achieved for air data systems. In the case of unmanned air vehicles, failure of any of air data sensors is more critical due to the absence of onboard pilot decision aid. This paper presents design of a dual redundancy air data system and the integration process for an unmanned air vehicle. The proposed dual-redundant architecture is based on two independent air data probes and redundancy management by central processing in two independent flight control computers. Starting from unit testing of single air data sensor, details are provided of system level tests used to meet overall requirements. Test results from system integration demonstrate the efficiency of the proposed process.

• Journal of KIISE
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• v.41 no.9
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• pp.605-610
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• 2014

Now, virtualization is no more emerging research area, and we can easily find its application in our circumstance. Nevertheless, I/O workloads are reluctant to be applied in virtual environment since they still suffer from unacceptable performance degradation due to virtualization latency. Many previous papers identified that virtual I/O overhead is mainly caused by exits and redundant I/O stack, and proposed several techniques to reduce them. However, they still have some limitations. In this paper, we introduce a novel I/O virtualization framework which improves I/O performance by exploiting multicore architecture. We applied our framework to the virtual network, and it improves TCP throughput up to 169%, and decreases UDP latency up to 38% on the network with the 10Gbps NIC.