• 센서학회지
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• 제21권1호
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• pp.59-67
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• 2012

It was reported that the latest sensor technology allow an 65536 conductive polymer sensor array to be made with broad but overlapping selectivity to different families of chemicals emulating the characteristics found in biological olfaction. However, the supernumerary redundancy always accompanies great error and risk as well as an inordinate amount of computation time and local minima in signal processing, e.g. neural networks. In this paper, we propose a new method to reduce the number of sensor for analysis by reducing redundancy between sensors and by removing unstable sensors using the cosine similarity method and to decide on representative sensor using FCM(Fuzzy C-Means) algorithm. The representative sensors can be just used in analyzing. And, we introduce DWT(Discrete Wavelet Transform) for data compression in the time domain as preprocessing. Throughout experimental trials, we have done a comparative analysis between gas sensor data with and without reduced redundancy. The possibility and superiority of the proposed methods are confirmed through experiments.

• 한국산업융합학회 논문집
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• 제24권6_2호
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• pp.827-839
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• 2021

Due to climate change and population growth, water scarcity is getting worse all over the world. Among various methods for desalination of seawater, the Multi-Effect Adsorptive Desalination method, which combines the existing Multi-Effect Desalination method and the Adsorptive Desalination method and can produce high-concentration-high-concentration freshwater, is emerging. Because the Multi-Effect Adsorptive Desalination method combines the two different methods, the system becomes complicated and the possibility of failure increases. Therefore, in this study, availability analysis was performed on the Multi-Effect Adsorptive Desalination process. A total of four types of reliability block diagrams were presented, and availability analysis was conducted based on them. The first form of a reliability block diagram is configured in series without any redundancy. The availability of the reliability block diagram composed of the serial system was found to be lower than the required availability. In order to increase availability, the redundancy to pumps and boiler are added to system. As a result of availability analysis, it was confirmed that designing desalination systems with redundancy to pump meets the 93% availability, which is typically required availability for various plants.

• 한국정보통신학회논문지
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• 제20권9호
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• pp.1717-1722
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• 2016

가용도는 사용자에게 고가용 서비스를 제공하는 네트워크 시스템의 주요 성능지표로서 임의의 시간에 사용자에게 서비스를 제공할 수 있는 확률이다. 네트워크 서비스의 가용도를 향상시키는 대표적인 방법으로 다중화 방식과 재활기법이 있다. 본 논문에서는 2N redundancy와 시간 기반의 재활기법이 가용도에 미치는 영향을 분석한다. 2N redundancy는 active 시스템과 standby 시스템으로 구성하는 다중화 방식이다. 재활주기에 의존하는 시간기반의 재활기법이다. 본 논문은 시간기반의 재활기법을 적용한 2N redundnacy모델을 stochastic reward net으로 설계한다. 설계한 모델은 stochastic Petri net package를 이용하여 분석한다. 수치해석을 통해 재활기법을 적용한 시스템의 가용도가 적절한 주기에서 재활기법을 적용하지 않은 시스템의 가용도보다 높다는 것을 알 수 있다.

• 대한토목학회논문집
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• 제26권4A호
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• pp.611-620
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• 2006

강합성 플레이트 2-거더교는 피로균열에 의해 한 개의 거더에 심각한 손상이 발생되는 경우 교량의 붕괴가 유발되는 단재 하경로 구조로 인식되고 있다. 본 논문에서는 강합성 2-거더교의 거더 손상시 교량의 여유도를 평가하기 위한 해석적 연구를 수행하였다. 여유도 평가는 단경간 및 3경간 연속교를 대상으로 하였으며, 수직브레이싱은 I-단면 가로보로 적용하고 하부 수평브레이싱이 설치되는 경우와 설치되지 않는 경우를 고려하였다. 정상 상태 및 손상 상태의 교량에 대해 하부 수평브레이싱의 유 무에 따른 내하 성능을 재료 및 기하비선형 해석으로 구하고 각 경우의 여유도를 비교 평가하였다. 해석 결과에 따르면 정상 상태의 2-거더 교량은 단순교와 연속교 모두 수평브레이싱이 없어도 여유도가 충분하며, 손상 상태의 교량에서는 수평브레이싱이 여유도 향상에 중요한 역할을 하는 것으로 분석되었다.

• 정보처리학회논문지:컴퓨터 및 통신 시스템
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• 제3권5호
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• pp.129-140
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• 2014

기존의 메모리에서 발생하는 다양한 고장들을 검출하기 위한 기법으로 BIST(Built-in self test)가 있고 고장이 검출되면 Spare를 할당하여 수리하는 BIRA(Built-in redundancy analysis)가 있다. 그리고 BIST와 BIRA를 통합한 형태인 BISR(Built-in self repair)를 통해 전체 메모리의 수율을 증가시킬 수 있다. 그러나 이전에 제안된 기법들은 RAM을 위해 제안된 기법으로 RAM의 메모리 구조와 특성이 다른 NAND-형 플래시 메모리에 사용하기에는 NAND-형 플래시 메모리의 고유 고장인 Disturbance를 진단하기 어렵다. 따라서 본 논문에서는 NAND-형 플래시 메모리에서 발생하는 Disturbance 고장을 검출하고 고장의 위치도 진단할 있는 BISD(Built-in self diagnosis)와 고장 블록을 수리할 수 있는 BISR을 제안한다.

• 상하수도학회지
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• 제11권1호
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• pp.21-32
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• 1997

Optimum design of water distribution network(WDN) in many times means just reducing redundancy. Given only a few situations are taken into consideration for such design, WDN deprived of inherited redundancy may not work properly in some unconsidered cases. Quantifying redundancy and incorporating it into the optimal design process will be a way of overcoming just reduction of redundancy. Expected shortage is developed as a reliability surrogate in WDN. It is an indicator of the frequency, duration and severity of failure. Using this surrogate, Expected Shortage Optimization Model (ESOM) is developed. ESOM is tested with an example network and results are analyzed and compared with those from other reliability models. The analysis results indicate that expected shortage is a quantitative surrogate measure, especially, good in comparing different designs and obtaining tradeoff between cost and. reliability. In addition, compared other models, ESOM is also proved useful in optimizing WDN with reliability and powerful in controlling reliability directly in the optimization process, even if computational burden is high. Future studies are suggested which focus on how to increase applicability and flexibility of ESOM.

• 전기학회논문지
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• 제63권12호
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• pp.1640-1648
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• 2014

This paper proposes a switching frequency reduction method for MMC (Modular Multilevel Converter) utilizing redundancy operation of sub-module, which can offer reduction of voltage harmonics and switching loss. The feasibility of proposed method was verified through computer simulations with PSCAD/EMTDC software. Based on simulation analysis, a hardware scaled-model of 10kVA, DC-1000V MMC was designed and manufactured in the lab. Various experiments were conducted to verify the feasibility of proposed method in the actual hardware system. The hardware scaled-model can be effectively utilized for analyzing the performance of MMC according to the modulation scheme and redundancy operation.

• 한국품질경영학회:학술대회논문집
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• 한국품질경영학회 1998년도 The 12th Asia Quality Management Symposium* Total Quality Management for Restoring Competitiveness
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• pp.393-403
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• 1998

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problemes presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the problems associated with these techniques.

• 산업경영시스템학회지
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• 제22권53호
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• pp.111-120
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• 1999

The advent of very large scale integration(VLSI) has had a tremendous impact on the design of fault-tolerant circuits and systems. The increasing density, decreasing power consumption, and decreasing costs of integrated circuits, due in part to VLSI, have made it possible and practical to implement the redundancy approaches used in fault-tolerant computing. The purpose of this paper is to study the many aspects of designing fault-tolerant systems in a VLSI environment. First, we expound upon the opportunities and problems presented by VLSI technology. Second, we consider in detail the importance of design mistakes, common-mode failures, and transient faults in VLSI. Finally, we examine the techniques available to implement redundancy using VLSI and the promlems associated with these techniques.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 전력전자학술대회 논문집
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• pp.209-210
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• 2014

In this paper, a hardware prototype for the 10kVA 11-level MMC was built and various experimental works were conducted to verify the operation algorithms of MMC. The hardware prototype was designed using computer simulation with PSCAD/EMTDC software. After manufactured in the lab, the hardware prototype was tested to verify the modulation algorithms to form the output voltage, the balancing algorithm to equalize the sub-module capacitor voltage, and the redundancy operation algorithm to improve the system reliability.