• 한국시뮬레이션학회논문지
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• 제18권4호
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• pp.59-66
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• 2009

VLSI(Very Large Scale Integration)와 WSI(Wafer Scale Integration)와 같은 통합기술로 인해 큰 용량의 메모리 대량생산이 가능 하게 된 지금 Redundancy는 메모리 칩의 제조와 결함이 있는 셀을 지닌 디바이스를 치료하는데 광범위하게 사용되어져왔다. 메모리칩의 밀도가 증가함에 따라 결함의 빈도 또한 증가한다. 많은 결함이 있다면 어쩔 수 없겠지만 적은 결함이 발생한 경우에는 해당 다이를 reject 시키는 것 보다는 수선해서 사용하는 것이 메모리생산 업체 입장에서는 보다 효율적이고 원가 절감 차원에서 필수적이다. 이와 같은 이유로 laser repair라는 공정이 필요하고 laser repair공정의 정확한 타깃을 설정하기 위해 redundancy analysis가 필요하게 되었다. CRA시뮬레이션은 기존의 redundancy analysis 알고리즘의 개념에서 벗어나 결함 유형별로 시뮬레이션한 후 RA를 진행함으로써 RA에 소요되는 시간을 절약함으로써 원가 경쟁력 강화를 할 수 있다.

• 대한임베디드공학회논문지
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• 제12권3호
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• pp.169-176
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• 2017

To replace conventional DRAM, many researches have been done on nonvolatile memories. The DRAM&PCM hybrid memory is one of the effective structure because it can utilize an advantage of DRAM and PCM. However, in order to use this characteristics, pages can be replaced frequently between DRAM and PCM. Therefore, PCM still has major problem that has write-limits. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an average access time and write count of PCM by utilizing two locality for an effective page replacement. We proposed a page selection algorithm which is recently requested to write in DRAM and an algorithm witch uses two locality in PCM. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM write count by around 22% and the average access time by 31% given the same PCM size, compared with CLOCK-DWF algorithm.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.388-388
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• 2012

In this letter, We have investigated cell characteristics of the alloy FePt-NDs charge trapping memory capacitors with high-k $Al_2O_3$ dielectrics as a blocking oxide. The capacitance versus voltage (C-V) curves obtained from a representative MOS capacitor embedded with FePt-NDs synthesized by the post deposition annealing (PDA) treatment process exhibit the window of flat-band voltage shift, which indicates the presence of charge storages in the FePt-NDs. It is shown that NDs memory with high-k $Al_2O_3$ as a blocking oxide has performance in large memory window and low leakage current when the diameter of ND is below 2 nm. Moreover, high-k $Al_2O_3$ as a blocking oxide increases the electric field across the tunnel oxide, while reducing the electric field across the blocking layer. From this result, this device can achieve lower P/E voltage and lower leakage current. As a result, a FePt-NDs device with high-k $Al_2O_3$ as a blocking oxide obtained a~7V reduction in the programming voltages with 7.8 V memory.

• 대한임베디드공학회논문지
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• 제13권3호
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• pp.151-160
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• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.120-121
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• 2007

Nano-floating gate memory (NFGM) devices were fabricated by using the low temperature poly-Si thin films crystallized by ELA and the $In_2O_3$ nano-particles embedded in polyimide layers as charge storage. Memory effect due to the charging effects of $In_2O_3$ nano-particles in polyimide layer was observed from the TFT NFGM. The post-annealing in 3% diluted hydrogen $(H_2/N_2)$ ambient improved the retention characteristics of $In_2O_3$ nano-particles embedded poly-Si TFT NFGM by reducing the interfacial states as well as grain boundary trapping states.

• 한국멀티미디어학회논문지
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• 제12권12호
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• pp.1710-1717
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• 2009

Flash memory has become the most important storage media in mobile devices along with its attractive features such as low power consumption, small size, light weight, and shock resistance. However, a flash memory can not be written before erased because of its erase-before-write characteristic, which lead to some garbage collection when there is not enough space to use. In this paper, we propose a novel garbage collection scheme, called block-level buffer garbage collection. When it is need to do merge operation during garbage collection, the proposed scheme does not merge the data block and corresponding log block but also search the block-level buffer to find the corresponding block which will be written to flash memory in the next future, and then decide whether merge it in advance or not. Our experimental results show that the proposed technique improves the flash performance up to 4.6% by reducing the unnecessary block erase numbers and page copy numbers.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.363-369
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• 2017

Phase-change random access memory (PRAM) has been emerged as a potential memory due to its excellent scalability, non-volatility, and random accessibility. But, as the cell current is reducing due to cell size scaling, the read-sensing window margin is also decreasing due to increased variation of cell performance distribution, resulting in a substantial loss of yield. To cope with this problem, a novel adaptive read-sensing reference current generation scheme is proposed, whose trimming range and resolution are adaptively controlled depending on process conditions. Performance evaluation in a 58-nm CMOS process indicated that the proposed read-sensing reference current scheme allowed the integral nonlinearity (INL) to be improved from 10.3 LSB to 2.14 LSB (79% reduction), and the differential nonlinearity (DNL) from 2.29 LSB to 0.94 LSB (59% reduction).

• 재활치료과학
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• 제6권2호
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• pp.71-83
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• 2017

Objective: This study was to develop and verify the effects of the exercise-cognitive combined dual-task training program on cognitive function and depression of the elderly with mild cognitive impairment(MCI). Methods: The subjects were randomly assigned to the exercise-cognitive combined dual-task training group(n=32) or single-task training group(n=31). To identify the effects on cognitive function, general cognitive function, frontal lobe function, and attention/working memory were measured. Depression was evaluated using Korean version of Geriatric Depression Scale. The outcome measurements were performed before and after the 8 weeks of intervention(2 days per week). Results: After 8 weeks, general cognitive function, frontal cognitive function, attention/working memory function, depression of the dual-task training group were significantly increased than those of the single-task training group(p<0.05). Conclusion: The results indicated that an exercise-cognitive combined dual-task training for MCI was effective in improving general cognitive function, frontal /executive function, attention/working memory function and reducing depression.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.385-386
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• 2008

Reducing the PR(Photoresist) dispense Rate is one of the important issues in Photolithography. It is a main concern that variation in PR dispense rate and existance of microbubble. so we need to measure the photoresist dispense rate more precisely. This paper presented a noble sensor of measuring the PR dispense and detecting the microbubble.

• IEIE Transactions on Smart Processing and Computing
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• 제4권2호
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• pp.78-82
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• 2015

General-purpose graphics processing units (GPGPUs) provide tremendous computational and processing power. Despite the latency hiding mechanism, a GPU architecture requires high memory bandwidth and lower latency between computational units and the memory system. For this reason, the current GPU architecture has private L1 caches in each core and a shared L2 cache to increase performance by reducing memory latency. But in some cases, this CPU-like cache design is not suitable for GPGPUs. In this paper, we analyze detailed cache performance related to GPGPU application characteristics, and suggest technical alternatives for the GPGPU architecture as future work.