• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.316-324
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• 2010

In this paper, we design a 256 kbits EEPROM for a MCU (Microcontroller unit) with the wide voltage range of 1.8 V to 5.5 V. The memory space of the EEPROM is separated into a program and data region. An option memory region is added for storing user IDs, serial numbers and so forth. By making HPWs (High-voltage P-wells) of EEPROM cell arrays with the same bias voltages in accordance with the operation modes shared in a double word unit, we can reduce the HPW-to-HPW space by a half and hence the area of the EEPROM cell arrays by 9.1 percent. Also, we propose a page buffer circuit reducing a test time, and a write-verify-read mode securing a reliability of the EEPROM. Furthermore, we propose a DC-DC converter that can be applied to a MCU with the wide voltage range. Finally, we come up with a method of obtaining the oscillation period of a charge pump. The layout size of the designed 256 kbits EEPROM IP with MagnaChip's 0.18 ${\mu}m$ EEPROM process is $1581.55{\mu}m{\times}792.00{\mu}m$.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.10
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• pp.1508-1515
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• 2017

This paper proposes the defect detection method for automatic inspection machines in printed circuit boards (PCBs) manufacturing system. The defects of PCB such as open, short, pin hole and scratch can be detected by comparing the standard image and the target image. The standard image is obtained from CAD file such as ODB++ format, and the target image is obtained by arranging, filtering and binarization of captured PCB image. Since the PCB size is too large and image resolution is too high, the image processing requires a lot of memory and computational time. The wavelet transform is applied to compress the standard and target images, which results in reducing the memory and computational time. To increase the inspection accuracy, we utilize the he HH-domain as well as LL-domain of the transformed images. Experimental results are finally presented to show the performance improvement of the proposed method.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.1
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• pp.1-6
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• 2016

Micromanufacturing is a useful system for reducing energy consumption. For micromanufacturing, tool clamping and workpiece clamping are important components to realize the machining process. Therefore, a shape memory alloy (SMA) ring type tool holder is developed. In addition, this holder needs cooling and heating processes to execute the tool clamping process. This study suggests a cooling/heating device based on peltier elements. The device will be applied to the heating/cooling process of an automatic tool changer (ATC) for the SMA tool holder. This study introduces the configuration and operating principle of the proposed ATC system. The description and prototype evaluation of this system were given. Plastic bolt and aluminum block were selected to enhance the cooling performance, and the installed tool was changed in 17 s during the experiments.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.194-203
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• 1998

In this paper, a new DCT-VQ method is proposed which can solve the problems of VQ such as the degradation of edge and enormous calculations. VQ is carried in DCT domain but spatial domain in order to protect the degradation of edge. DCT makes high correlated image data decorrelated and the energy concentrated on a few coefficients. In DCT domain, the DC coefficient is quantized with 8 bits uniform scalar quantizer and the AC coefficients are divided to three regions and coded with vector qiantizer for considering edge components. For the decrease of the calculation and memory, the vectors for three region have small dimension of $1{\times}7$ and use the same codebook. Thus, the proposed method can fully express the edge components by considering AC coefficients in DCT domain and decrease the calculation and memory be reducing the dimension of vectors.

• Electrical & Electronic Materials
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• v.9 no.5
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• pp.476-482
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• 1996

The multi-dielectric layer SiO$_{2}$/Si$_{3}$N$_{4}$/SiO$_{2}$(ONO) is used to improve electrical capacitance and to scale down the memory device. In this paper, improvement of the capacitance by reducing the bottom oxide thickness in the nitride deposition with load lock(L/L) vacuum system is studied. Bottom oxide thickness under the nitride layer is measured by ellipsometer both in L/L and non-L/L systems. Both results are in the range of 3-10.angs. and 10-15.angs., respectively, independent of the nitride and top oxide thickness. Effective thickness and cell capacitance for SONOS capacitor are in the range of 50-52.angs. and 35-37fF respectively in the case of nitride 70.angs. in L/L vacuum system. Compared with non-L/L system, the bottom oxide thickness in the case of L/L system decreases while cell capacitance increases about 4 fF. The results obtained in this study are also applicable to ONO scaling in the thin bottom oxide region of memory stacked capacitor.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.12
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• pp.4776-4798
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• 2015

The location selection of virtual machines in distributed cloud is difficult because of the physical resource distribution, allocation of multi-dimensional resources, and resource unit cost. In this study, we propose a multi-object virtual machine location selection algorithm (MOVMLSA) based on group information, doubly linked list structure and genetic algorithm. On the basis of the collaboration of multi-dimensional resources, a fitness function is designed using fuzzy logic control parameters, which can be used to optimize search space solutions. In the location selection process, an orderly information code based on group and resource information can be generated by adopting the memory mechanism of biological immune systems. This approach, along with the dominant elite strategy, enables the updating of the population. The tournament selection method is used to optimize the operator mechanisms of the single-point crossover and X-point mutation during the population selection. Such a method can be used to obtain an optimal solution for the rapid location selection of virtual machines. Experimental results show that the proposed algorithm is effective in reducing the number of used physical machines and in improving the resource utilization of physical machines. The algorithm improves the utilization degree of multi-dimensional resource synergy and reduces the comprehensive unit cost of resources.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.3
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• pp.89-99
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• 1995

In this paper, we ecamined the effect that MCM-L technique influencess on the design and fabrication of multichip memory modules in increasing the packing desity of memory capacity and maximizing its electrical characteristics. For that purpose, we examined the effective methods of reducing the area of module layout and the wiring length with the variation of chip allocation and the number of wiring layers. We fabricated a 256K${\times}$8bit SRAM module with eight 32K${\times}$8bit SRAM chips. The routing experiment showed that we could optimize the area of module layout and wiring length by placing chips in a row, arranging module I/O pads parallel to chip I/O pads, and equalizing the number of terminal sides of module I/O's to that of chip I/O's. The routing was optimized when we used three wire layers in case of one sided chip mounting or five wire layers in case of double sided chip mounting. The fabricated modules showed 18.9 cm/cm$^{2}$ in wiring density, 65 % in substrate occupancy efficiency, and module substrate and functionally tested to find out the module working perfectly.

• Korean Journal of Adult Nursing
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• v.27 no.6
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• pp.707-717
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• 2015

Purpose: This study was to develop and verify the effects of the exercise-cognitive combined dual-task training program on cognitive function and depression of the elderly with mild cognitive impairment (MCI). Methods: A non-equivalent control group pretest-posttest design was used. The participants were assigned into two groups: an experimental group receiving an exercise-cognitive combined dual-task (n=20) and a control group receiving a simple-task (n=18). After 8 weeks of intervention (2 days per week), the change in depression and cognitive functions were compared between the groups. Results: General cognitive function (t=-2.81, p=.011), frontal cognitive function (Z=-3.50, p<.001), attention/working memory function (U=-2.91, p=.004), depression (t=4.96, p<.001) of the experimental group were significantly increased than those of the control group. Conclusion: The findings of the study showed that an exercise-cognitive combined dual-task program for MCI was effective in improving general cognitive function, frontal and executive function, attention/working memory function, and reducing depression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1045-1051
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• 2003

The SOVA, which produces the soft decision value, can be used as a sub-optimum solution for concatenated codes such as turbo codes, since it is computationally efficient compared with the optimum MAP algorithm. In this paper, we propose an efficient implementation of the SOVA used for decoding turbo codes, by reducing the number of calculations for soft decision values and trace-back operations. In order to utilize the memory efficiently, the whole block of turbo codes is divided into several sub-blocks in the proposed algorithm. It is demonstrated that the proposed algorithm requires less computation than the conventional algorithm, while providing the same overall performance.