• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.139-144
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• 2019

For recent decades, Non-volatile Memory (NVM) technologies have been drawing a high attention both in industry and academia due to its high density and short latency comparable to that of DRAM. However, NVM devices has write endurance problem and thus the current data structures that have been built around DRAM-specific features including unlimited program cycles is inadequate for NVM, reducing the device lifetime significantly. In this paper, we revisit a red-black tree extensively adopted for data indexing across a wide range of applications, and make it to better fit for NVM. Specifically, we observe that the conventional red-black tree wears out the specific location of memory because of its rebalancing operation to ensure fast access time over a whole dataset. However, this rebalancing operation frequently updates the long-lived nodes, which leads to the skewed wear out across the NVM cells. To resolve this problem, we present a new swapping wear-leveling red-black tree that periodically moves data in the worn-out node into the young node. The performance study with real-world traces demonstrates the proposed red-black tree reduces the standard deviation of the write count across nodes by up to 12.5%.

• Journal of Korea Spatial Information System Society
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• v.8 no.1 s.16
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• pp.77-92
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• 2006

This paper proposes an efficient spatial data manager for map services in mobile environment. It is designed to provide interoperability and efficient performance at once. To provide interoperability and reusability, the spatial data manager conforms to international standards such as the OpenGIS Simple Features Implementation Specification for OLE/COM, OpenGIS Geography Markup Language (GML) Encoding Specification developed by the Open Geospatial Consortium (OGC). The spatial data manger exploits physical main memory using Address Windowing Extensions supported by Microsoft Windows to manage spatial data for efficient performance by reducing time to read data from disk on user's request. The format of the spatial data in main memory is target data (GML) to reduce conversion time from source data to it. Progressive transmission is also provided to reduce latency time by representing only received partial data for mobile environment without waiting whole transmission.

• The Journal of Society for e-Business Studies
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• v.15 no.4
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• pp.21-31
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• 2010

Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

• Korean Institute of Interior Design Journal
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• v.15 no.6 s.59
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• pp.43-51
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• 2006

The purpose of this study is to present possibility about applying space design of urban theory focused on collective memory. Urban which is the final data of human's collective life has been recognized creative circumstances human collective is living. It can not think without collective from its motivation to problem of form as well as building as element which compose these cities. It is to recognize essential attribute of construction in the collective that think architecture with urban, and It means that recognize actuality of architecture that can talk as the most collective product that represent human. There was discussion for collective and urban. But, this problem was proceeded to clear human knowledge of architecture mainly in other discipline, and even if speak as field of architecture, it could just pass confined meaning by refering at process that clear several main aspects of architecture as doing not pass over more than it. Problem of form that is ultimate aspect of architecture remained by different thing still doing not combine with collective architecture, and occasionally happened the case that make collective of architecture and relation of form overly incommodiously reducing form by a tool for diagram, shape, figuration in the aspect of collective. This research study concept for memory collective in the urban and collective of architecture, and choose urban planning methodology and their work by specific example between Aldo Rosi and Rem Koolhaas dealing with architecture and urban, and present possibility about space design of urban.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.419-428
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• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• Journal of IKEEE
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• v.25 no.3
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• pp.479-484
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• 2021

This paper proposed and designed a structure to achieve high performance with a small number of cores in GPGPU with SIMT structure. GPGPU for application to mobile devices requires a structure to increase performance compared to power consumption. In order to reduce power consumption, the number of cores decreased, but to improve performance, the size of the warp scheduler for managing threads was set to 4, which was greatly reduced than 32 of general GPGPU. Reducing warp size can reduce the number of idle cycles in pipelines and efficiently apply memory latency to reduce miss penalty when accessing cache memory. The designed GPGPU measured computational performance using a test program that includes floating point operations and measured power consumption through a 28nm CMOS process to obtain 104.5GFlops/Watt as a performance per power. The results of this paper showed about four times better performance per power compared to Tegra K1 of Nvidia

• Structural Engineering and Mechanics
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• v.82 no.1
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• pp.107-120
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• 2022

The bracing members capable of active control against seismic loads to reduce earthquake damage have been widely utilized in construction projects. Effectively reducing the structural damage caused by earthquake events, bracing systems equipped with retrofitting damper devices, which take advantage of the energy dissipation and impact absorption, have been widely used in practical construction sites. Shape Memory Alloys (SMAs) are a new generation of smart materials with the capability of recovering their predefined shape after experiencing a large strain. This is mainly due to the shape memory effects and the superelasticity of SMA. These properties make SMA an excellent alternative to be used in passive, semi-active, and active control systems in civil engineering applications. In this research, a new system in diagonal braces with slit damper combined with SMA is investigated. The diagonal element under the effect of tensile and compressive force turns to shear force in the slit damper and creates tension in the SMA. Therefore, by creating shear forces in the damper, it leads to yield and increases the energy absorption capacity of the system. The purpose of using SMA, in addition to increasing the stiffness and strength of the system, is to create reversibility for the system. According to the results, the highest capacity is related to the case where the ratio of the width of the middle section to the width of the end section (b₁/b) is 1.0 and the ratio of the height of the middle part to the total height of the damper (h₁/h) is 0.1. This is mainly because in this case, the damper section has the highest cross-section. In contrast, the lowest capacity is related to the case where b₁/b=0.1 and the ratio h₁/h=0.8.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.2
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• pp.345-351
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• 2023

As software development progresses and programs become increasingly complex, the cost of reducing and managing software vulnerabilities has also increased. To address this issue, the Rust programming language, which guarantees Memory Safety, has been suggested as an alternative for more error-prone languages such as traditional C/C++. However, Rust also supports the use of libraries written in C/C++ to enhance compatibility with older languages and avoid redundant development, compromising its original guarantees. For example, memory corruption happened in C/C++ can lead to exploits such as buffer overflow, Use-After-Free and null-pointer dereferecing. To tackle this problem, recent studies have been conducted to secure interactino between Rust and C/C++ by isolation. This paper uncovers areas that have not been fully explored in previous studies, following limitation analysis on each. Finally, this paper suggests the future direction of research on safe interaction between Rust and C/C++.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.163-168
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• 2015

Many IP address lookup approaches employ Bloom filters to obtain a high-speed search performance. Especially, it has been recently studied that the search performance of trie-based algorithms can be significantly improved by adding Bloom filters. In such algorithms, the number of trie accesses can be greatly reduced because Bloom filters can determine whether a node exists in a trie without actually accessing the trie. Bloom filters do not have false negatives but have false positives. False positives can lead to unnecessary trie accesses. The false positive rate must thus be reduced to enhance the performance of lookup algorithms applying Bloom filters. One important characteristic of trie-based algorithms is that all the ancestors of a node are also stored. The proposed algorithm utilizes this characteristic in reducing the false positive rate of a Bloom filter without increasing the size of the memory for the Bloom filter. When a Bloom filter produces a positive result for a node of a trie, we propose to check whether the ancestors of the node are also positives. Because Bloom filters have no false negatives, the negatives of any of the ancestors mean that the positive of the node is false. In other words, we propose to use more Bloom filter queries to reduce the false positive rate of a Bloom filter in trie-based algorithms. Simulation results show that querying one ancestor of a node can reduce the false positive rate by up to 67% with exactly the same architecture and the same memory requirement. The proposed approach can be applied to other trie-based algorithms employing Bloom filters.

• Journal of Power Electronics
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• v.11 no.2
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• pp.228-236
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• 2011

The ${\Delta}\;V_{10}$ or 10-Hz flicker index, as a common method of measurement of voltage flicker severity in power systems, requires a high computational cost and a large amount of memory. In this paper, for measuring the ${\Delta}\;V_{10}$ index, a new method based on the Adaline (adaptive linear neuron) system, the FFT (fast Fourier transform), and the PSO (particle swarm optimization) algorithm is proposed. In this method, for reducing the sampling frequency, calculations are carried out on the envelope of a power system voltage that contains a flicker component. Extracting the envelope of the voltage is implemented by the Adaline system. In addition, in order to increase the accuracy in computing the flicker components, the PSO algorithm is used for reducing the spectral leakage error in the FFT calculations. Therefore, the proposed method has a lower computational cost in FFT computation due to the use of a smaller sampling window. It also requires less memory since it uses the envelope of the power system voltage. Moreover, it shows more accuracy because the PSO algorithm is used in the determination of the flicker frequency and the corresponding amplitude. The sensitivity of the proposed method with respect to the main frequency drift is very low. The proposed algorithm is evaluated by simulations. The validity of the simulations is proven by the implementation of the algorithm with an ARM microcontroller-based digital system. Finally, its function is evaluated with real-time measurements.