• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2005.05a
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• pp.144-149
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• 2005

In recent years, as the robot technology is developed the researches on the artificial muscle actuator that enable robot to move dextrously like biological organ become active. The widely used materials for artificial muscle are the shape memory alloy and the electroactive polymer. These actuators have the higher energy density than the electromechanical actuator such as motor. However, there are some drawbacks for actuator. SMA has the hysterical dynamic characteristics. In this paper the segmented binary control for reducing the hysteresis of SMA is proposed and the simulation of anthropomorphic robotic hand is performed using ADAMS.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.10a
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• pp.310-313
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• 2005

In recent years, as the robot technology is developed, the researches on the artificial muscle actuator that enable robot to move dexterously like biological organ become active. The widely used materials for artificial muscle are the shape memory alloy and the electro-active polymer. These actuators have the higher energy density than the electro-mechanical actuator such as motor. However, there are some drawbacks for actuator. SMA has the hysterical dynamic characteristics. In this paper, the simulation of anthropomophic robotic hand is performed using ADAMS and the segmented binary control for reducing the hysteresis of SMA is proposed. SMA is controlled by thermo-electric module. The relations between the force and the hysteresis are developed to verify the validity of the suggested method.

• Computers and Concrete
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• v.23 no.5
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• pp.311-320
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• 2019

The substructuring technique is one of the efficient methods for reducing computational effort and memory usage in the finite element method, especially in large-scale structures. Proper mesh partitioning plays a key role in the efficiency of the technique. In this study, new algorithms are proposed for mesh partitioning based on an element search technique. The computational cost function is optimized by aligning each element of the structure to a proper substructure. The genetic algorithm is employed to minimize the boundary nodes of the substructures. Since the boundary nodes have a vital performance on the mesh partitioning, different strategies are proposed for the few number of substructures and higher number ones. The mesh partitioning is optimized considering both computational and memory requirements. The efficiency and robustness of the proposed algorithms is demonstrated in numerous examples for different size of substructures.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1254-1264
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• 2008

This paper suggests an extended memory polynomial model that improves accuracy in modeling memory effects of RF power amplifiers(PAs), and verifies effectiveness of the suggested method. The extended memory polynomial model includes cross-terms that are products of input terms that have different delay values to improve the limited accuracy of basic memory polynomial model that includes the diagonal terms of Volterra kernels. The complexity of the memoryless model, memory polynomial model, and the suggested model are compared. The extended memory polynomial model is represented with a matrix equation, and the Volterra kernels are extracted using least square method. In addition, the structure of digital predistorter and digital signal processing(DSP) algorithm based on the suggested model and indirect learning method are proposed to implement a digital predistortion linearization. To verify the suggested model, the predicted output of the model is compared with the measured output for a 10W GaN HEMT RF PA and 30 W LDMOS RF PA using 2.3 GHz WiBro input signal, and adjacent-channel power ratio(ACPR) performance with the proposed digital predistortion is measured. The proposed model increases model accuracy for the PAs, and improves the linearization performance by reducing ACPR.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.2
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• pp.151-158
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• 2016

The HSA resolves an old problem with existing CPU and GPU architectures by allowing both units to directly access each other's memory pools via unified virtual memory. In a physically realized system, however, frequent data exchanges between CPU and GPU for a virtual memory block result bottlenecks and coherence request overheads. In this paper, we propose Fusion Processor Architecture for efficient access of main memory from both CPU and GPU. It consists of Job Manager, Re-mapper, and Pre-fetcher to control, organize, and distribute work loads and working areas for GPU cores. These components help on reducing memory exchanges between the two processors and improving overall efficiency by eliminating faulty page table requests. To verify proposed algorithm architectures, we develop an emulator based on QEMU, and compare several architectures such as CUDA(Compute Unified Device Architecture), OpenMP, OpenCL. As a result, Proposed fusion processor architectures show 198% faster than others by removing unnecessary memory copies and cache-miss overheads.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.609-611
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• 2006

This paper describes a CMOS sub-bandgap reference using Pseudo-Resistors which can be widely used in flash memory, DRAM, ADC and Power management circuits. Bandgap reference circuit operates weak inversion for reducing power consumption and uses Pseudo-Resistors for reducing the chip area, instead of big resistor. It is implemented in 0.35um Standard 1P4M CMOS process. The temperature coefficient is 5ppm/$^{\circ}C$ from $40^{\circ}C$ to $100^{\circ}C$ and minimum power supply voltage is 1.2V The core area is 1177um${\times}$617um. Total current is below 2.8uA and output voltage is 0.598V at $27^{\circ}C$.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.289-292
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• 2000

This paper proposes a new FIR fillet architecture for the spectral shaping filter used in the transmitter and the receiver for QAM-VDSL modem. This architecture reduced the hardware property and the power consumption. We derive algorithms for reducing the number of multipliers and the memory architecture for reducing the power consumption. The proposed filter has been implemented using VHDL and performed functional simulation.

• Journal of Korean Institute of Industrial Engineers
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• v.22 no.4
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• pp.567-578
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• 1996

In relational databases the number of disk accesses depends on the amount of data transferred from disk to main memory for processing the transactions. N-ary vertical partitioning of the relation can often result in a decrease in the number of disk accesses, since not all attributes in a tuple are required by each transactions. In this paper, a 0-1 integer programming model for solving n-ary vertical partitioning problem minimizing the number of disk accesses is formulated and a branch-and-bound method is used to solve it. A preprocessing procedure reducing the number of variables is presented. The algorithm is illustrated with numerical examples and is shown to be computationally efficient. Numerical experiments reveal that the proposed method is more effective in reducing access costs than the existing algorithms.