1 |
T. Chilimbi, B. Davison, and J. Larus. Cache-Conscious Structure Definition. Proceedings of the ACM SIGPLAN 1999 conference on Programming Language Design and Implementation, pp.13-24, 1999
DOI
|
2 |
T. Chilimbi, M. Hill, and J. Larus. Cache-conscious structure layout. 1986. In Proceedings of the ACM SICPLAN Conference on Programming Language Design and Implementation, pp.1-12, May 1999
DOI
|
3 |
T. Kistler and M. Franz. Automated data-member layout of heap objects to improve memory-hierarchy performance. ACM transactions on Programming Languages and Systems, Vol.22, No.3, pp.490-505, May 2000
DOI
ScienceOn
|
4 |
P. Panda, N. Dutt, and A. Nicolau. Memory Issues In Embedded Systems-On-Chip : Optimizations and Exploration. Kluwer Academic Publishers, 1999
|
5 |
P. Panda, F. Catthoor, N. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkrani, A. Vandercappelle, and P. Kjeldsberg. Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems, Vol.7, No.2, pp.149-206, April 2001
DOI
ScienceOn
|
6 |
D. N. Truong, F. Bodin, and A. Seznec, Improving cache behavior of dynamically allocated data structures. Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, p.322, 1998
DOI
|
7 |
R. M. Rabbah and K. V. Palem. Data Remapping for Design Space Optimization of Embedded Memory Systems. ACM Trans. On Embedded Computing Systems., Vol.2, No.2, pp.186-218, May 2003
DOI
|
8 |
P. Panda, N. Dutt, and A. Nicolau. Memory data reorganization for improved cache performance in embedded processor applications. ACM Transactions on Design Automation of Electronic Systems, Vol.2, No.4, pp.384-409, 1997
DOI
|