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Compact Field Remapping for Dynamically Allocated Structures  

Kim, Jeong-Eun (한국과학기술원 전산학과)
Han, Hwan-Soo (한국과학기술원 전산학과)
Abstract
The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.
Keywords
Data reorganization; field remapping;
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1 T. Chilimbi, B. Davison, and J. Larus. Cache-Conscious Structure Definition. Proceedings of the ACM SIGPLAN 1999 conference on Programming Language Design and Implementation, pp.13-24, 1999   DOI
2 T. Chilimbi, M. Hill, and J. Larus. Cache-conscious structure layout. 1986. In Proceedings of the ACM SICPLAN Conference on Programming Language Design and Implementation, pp.1-12, May 1999   DOI
3 T. Kistler and M. Franz. Automated data-member layout of heap objects to improve memory-hierarchy performance. ACM transactions on Programming Languages and Systems, Vol.22, No.3, pp.490-505, May 2000   DOI   ScienceOn
4 P. Panda, N. Dutt, and A. Nicolau. Memory Issues In Embedded Systems-On-Chip : Optimizations and Exploration. Kluwer Academic Publishers, 1999
5 P. Panda, F. Catthoor, N. Dutt, K. Danckaert, E. Brockmeyer, C. Kulkrani, A. Vandercappelle, and P. Kjeldsberg. Data and memory optimization techniques for embedded systems. ACM Transactions on Design Automation of Electronic Systems, Vol.7, No.2, pp.149-206, April 2001   DOI   ScienceOn
6 D. N. Truong, F. Bodin, and A. Seznec, Improving cache behavior of dynamically allocated data structures. Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, p.322, 1998   DOI
7 R. M. Rabbah and K. V. Palem. Data Remapping for Design Space Optimization of Embedded Memory Systems. ACM Trans. On Embedded Computing Systems., Vol.2, No.2, pp.186-218, May 2003   DOI
8 P. Panda, N. Dutt, and A. Nicolau. Memory data reorganization for improved cache performance in embedded processor applications. ACM Transactions on Design Automation of Electronic Systems, Vol.2, No.4, pp.384-409, 1997   DOI